Intel Xeon L3406 CM80616005010AA User Manual
Product codes
CM80616005010AA
System Address Map
292
Datasheet, Volume 2
PCI Express and DMI Interface read accesses to the GMADR range are not supported
therefore will have no address translation concerns. PCI Express and DMI Interface
reads to GMADR will be remapped to address 000C_0000h. The read will complete with
UR (unsupported request) completion status.
therefore will have no address translation concerns. PCI Express and DMI Interface
reads to GMADR will be remapped to address 000C_0000h. The read will complete with
UR (unsupported request) completion status.
GTT Fetches are always decoded (at fetch time) to ensure not in SMM (actually,
anything above base of TSEG or 640 KB – 1 MB). Thus, they will be invalid and go to
address 000C_0000h, but that isn’t specific to PCI Express or DMI; it applies to
processor or internal graphics engines. Also, since the GMADR snoop would not be
directly to the SMM space, there wouldn’t be a writeback to SMM. In fact, the writeback
would also be invalid (because it uses the same translation) and go to address
000C_0000h.
anything above base of TSEG or 640 KB – 1 MB). Thus, they will be invalid and go to
address 000C_0000h, but that isn’t specific to PCI Express or DMI; it applies to
processor or internal graphics engines. Also, since the GMADR snoop would not be
directly to the SMM space, there wouldn’t be a writeback to SMM. In fact, the writeback
would also be invalid (because it uses the same translation) and go to address
000C_0000h.
5.6
Memory Shadowing
Any block of memory that can be designated as read-only or write-only can be
“shadowed” into Processor DRAM memory. Typically this is done to allow ROM code to
execute more rapidly out of main DRAM. ROM is used as a read-only during the copy
process while DRAM at the same time is designated write-only. After copying, the
DRAM is designated read-only so that ROM is shadowed. Processor bus transactions are
routed accordingly.
“shadowed” into Processor DRAM memory. Typically this is done to allow ROM code to
execute more rapidly out of main DRAM. ROM is used as a read-only during the copy
process while DRAM at the same time is designated write-only. After copying, the
DRAM is designated read-only so that ROM is shadowed. Processor bus transactions are
routed accordingly.
5.7
IIO Address Map Notes
5.7.1
Memory Recovery
When software recovers an underlying DRAM memory region that resides below the
4-GB address line that is used for system resources like firmware, local APIC, and so
forth, (the gap below 4-GB address line), it needs to make sure that it does not create
system memory holes whereby all the system memory cannot be decoded with two
contiguous ranges. It is OK to have unpopulated addresses within these contiguous
ranges that are not claimed by any system resource. IIO decodes all inbound accesses
to system memory using two contiguous address ranges (0–TOLM, 4 GB–TOHM) and
there cannot be holes created inside of those ranges that are allocated to other system
resources in the gap below 4-GB address line. The only exception to this is the hole
created in the low system DRAM memory range using the VGA memory address. IIO
comprehends this and does not forward these VGA memory regions to system memory.
4-GB address line that is used for system resources like firmware, local APIC, and so
forth, (the gap below 4-GB address line), it needs to make sure that it does not create
system memory holes whereby all the system memory cannot be decoded with two
contiguous ranges. It is OK to have unpopulated addresses within these contiguous
ranges that are not claimed by any system resource. IIO decodes all inbound accesses
to system memory using two contiguous address ranges (0–TOLM, 4 GB–TOHM) and
there cannot be holes created inside of those ranges that are allocated to other system
resources in the gap below 4-GB address line. The only exception to this is the hole
created in the low system DRAM memory range using the VGA memory address. IIO
comprehends this and does not forward these VGA memory regions to system memory.
5.7.2
Non-Coherent Address Space
IIO supports one coarse main memory range which can be treated as non-coherent by
IIO, that is, inbound accesses to this region are treated as non-coherent. This address
range has to be a subset of one of the coarse memory ranges that IIO decodes towards
system memory. Inbound accesses to the NC range are not snooped on Intel QuickPath
Interconnect.
IIO, that is, inbound accesses to this region are treated as non-coherent. This address
range has to be a subset of one of the coarse memory ranges that IIO decodes towards
system memory. Inbound accesses to the NC range are not snooped on Intel QuickPath
Interconnect.