Intel Xeon L3406 CM80616005010AA User Manual
Product codes
CM80616005010AA
Datasheet, Volume 2
49
Processor Integrated I/O (IIO) Configuration Registers
3.3.3.25
PMBASEU—Prefetchable Memory Base (Upper 32 bits)
The Prefetchable Base Upper 32-bits and Prefetchable Limit Upper 32-bits registers are
extensions to the Prefetchable Memory Base and Prefetchable Memory Limit registers
to support a 64-bit prefetchable memory address range.
extensions to the Prefetchable Memory Base and Prefetchable Memory Limit registers
to support a 64-bit prefetchable memory address range.
3.3.3.26
PMLIMITU—Prefetchable Memory Limit (Upper 32 bits)
Register:
PMBASEU
Device: 3-6
(PCIe)
Function:
0
Offset:
28h
Bit
Attr
Default
Description
31:0
RW
00000000h
Prefetchable Upper 32-bit Memory Base Address
This field corresponds to A[63:32] of the memory address that maps to the
This field corresponds to A[63:32] of the memory address that maps to the
upper base of the prefetchable range of memory accesses that will be passed
by the PCI Express bridge. The OS should program these bits based on the
available physical limits of the system.
Register:
PMLIMITU
Device: 3-6
(PCIe)
Function:
0
Offset:
2Ch
Bit
Attr
Default
Description
31:0
RW
00000000h
Prefetchable Upper 32-bit Memory Limit Address
This field corresponds to A[63:32] of the memory address that maps to the
This field corresponds to A[63:32] of the memory address that maps to the
upper limit of the prefetchable range of memory accesses that will be passed
by the PCI Express bridge. OS should program these bits based on the
available physical limits of the system.