Intel Xeon L3406 CM80616005010AA User Manual
Product codes
CM80616005010AA
Processor Integrated I/O (IIO) Configuration Registers
52
Datasheet, Volume 2
3.3.4.3
SVID—Subsystem Vendor ID
3.3.4.4
SID—Subsystem Identity
3.3.4.5
DMIRCBAR—DMI Root Complex Register Block Base Address
Register
This is the base address for the root complex configuration space. This window of
addresses contains the Root complex Register set for the PCI Express hierarchy
associated with the processor. On Reset, the Root complex configuration space is
disabled and must be enabled by writing a 1 to DMIRCBAREN [Device 0, offset 50h,
bit 0]. All the bits in this register are locked in Intel TXT enabled mode.
addresses contains the Root complex Register set for the PCI Express hierarchy
associated with the processor. On Reset, the Root complex configuration space is
disabled and must be enabled by writing a 1 to DMIRCBAREN [Device 0, offset 50h,
bit 0]. All the bits in this register are locked in Intel TXT enabled mode.
Register:
SVID
Device: 3-6
(PCIe)
Function:
0
Offset:
44h
Bit
Attr
Default
Description
15:0
RWO
8086h
Subsystem Vendor Identification
This field is programmed during boot-up to indicate the vendor of the system
This field is programmed during boot-up to indicate the vendor of the system
board. After it has been written once, it becomes read only.
Register:
SID
Device: 3-6
(PCIe)
Function:
0
Offset:
46h
Bit
Attr
Default
Description
15:0
RWO
00h
Subsystem Identification Number
Assigned by the subsystem vendor to uniquely identify the subsystem.
Assigned by the subsystem vendor to uniquely identify the subsystem.
Register:
DMIRCBAR
Device:
0 (DMI)
Function:
0
Offset:
50h
Bit
Attr
Default
Description
31:12
RWO
00000h
DMI Base Address (DMIRCBAR)
This field corresponds to Bits 32:12 of the base address DMI Root Complex
This field corresponds to Bits 32:12 of the base address DMI Root Complex
register space. BIOS will program this register resulting in a base address for a
4-KB block of contiguous memory address space. This register ensures that a
naturally aligned 4-KB space is allocated within the first 64 GB of addressable
memory space. System Software uses this base address to program the DMI
Root Complex register set. All the Bits in this register are locked in Intel
Trusted Execution Technology (Intel TXT) enabled mode.
11:1
RV
00h
Reserved
0
RW
0
DMIRCBAR Enable (DMIRCBAREN)
0 = DMIRCBAR is disabled and does not claim any memory.
0 = DMIRCBAR is disabled and does not claim any memory.
1 = DMIRCBAR memory mapped accesses are claimed and decoded.