Intel Xeon L3406 CM80616005010AA User Manual
Product codes
CM80616005010AA
Datasheet, Volume 2
83
Processor Integrated I/O (IIO) Configuration Registers
3.3.5.5
CTOCTRL—Completion Time-out Control Register
1
RWO
0h
Inbound Configuration Enable
When clear, all inbound configuration transactions are sent a UR response
When clear, all inbound configuration transactions are sent a UR response
by the receiving PCI Express port. When set, inbound configs are allowed.
Note: Enabling is only for debug purposes.
Note: Enabling is only for debug purposes.
0
Dev:attr
0:RO
else:RW
Dev:val
0:1
else: 0
Set Host Bridge Class Code
When this bit is set, the class code register indicates “Host Bridge”.
When this bit is set, the class code register indicates “Host Bridge”.
Register:
CTOCTRL
Device:
0 (DMI), 3-6 (PCIe)
Function:
0
Offset:
1E0h
Bit
Attr
Default
Description
31:10
RV
00
Reserved
9:8
RW
00
XP-to-PCIe Time-out Select within 17 s to 64 s Range
When OS selects a time-out range of 17 s to 64 s for Windows* XP (that
When OS selects a time-out range of 17 s to 64 s for Windows* XP (that
affect NP tx issued to the PCI Express/DMI) using the root port’s DEVCTRL2
register, this field selects the sub-range within that larger range, for
additional controllability.
00 = 17 s-30 s
01 = 31 s-45 s
10 = 46 s-64 s
11 = Reserved
Note: This field is subject to redefinition based on design feedback.
00 = 17 s-30 s
01 = 31 s-45 s
10 = 46 s-64 s
11 = Reserved
Note: This field is subject to redefinition based on design feedback.
7:0
RV
00
Reserved
(Sheet 3 of 3)
Register: MISCCTRLSTS
Device:
0 (DMI), 3-6 (PCIe)
Function:
0
Offset:
188h
Bit
Attr
Default
Description