Intel Xeon L3406 CM80616005010AA User Manual
Product codes
CM80616005010AA
Processor Integrated I/O (IIO) Configuration Registers
90
Datasheet, Volume 2
3.3.6.10
DMIVC1RSTS—DMI VC1 Resource Status
Reports the Virtual Channel specific status.
3.3.6.11
DMILCAP—DMI Link Capabilities
Indicates DMI specific capabilities.
BAR: DMIRCBAR
Register:
DMIVC1RSTS
Offset: 0026h
Bit
Attr
Default
Description
15:2
RO
0h
Reserved. Reserved and Zero for future R/WC/S implementations. Software
must use 0 for writes to these bits.
1
RO
1
Virtual Channel 1 Negotiation Pending (VC1NP):
0 = The VC negotiation is complete.
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation (initialization or
disabling).
This bit indicates the status of the process of Flow Control initialization. It is
set by default on Reset, as well as whenever the corresponding Virtual
Channel is Disabled or the Link is in the DL_Down state.
It is cleared when the link successfully exits the FC_INIT2 state.
BIOS Requirement: Before using a Virtual Channel, software must check
It is cleared when the link successfully exits the FC_INIT2 state.
BIOS Requirement: Before using a Virtual Channel, software must check
whether the VC Negotiation Pending fields for that Virtual Channel are cleared
in both Components on a Link.
0
RO
0
Reserved
BAR: DMIRCBAR
Register:
DMILCAP
Offset: 0084h
Bit
Attr
Default
Description
31:18
RO
0h
Reserved
17:15
RWO
010
L1 Exit Latency (EL1)
Default value of 010b indicates that the exit latency is 2 µs to 4 µs.
Default value of 010b indicates that the exit latency is 2 µs to 4 µs.
14:12
RWO
7h
L0s Exit Latency
11:10
RO
11b
Active State Link PM Support (ASLPMS)
L0s and L1 entry supported.
L0s and L1 entry supported.
9:4
RO
04h
Max Link Width (MLW)
Indicates the maximum number of lanes supported for this link.
Indicates the maximum number of lanes supported for this link.
3:0
RO
1h
Max Link Speed (MLS)
Hardwired to indicate 2.5 Gb/s.
Hardwired to indicate 2.5 Gb/s.