Intel SU2300 AV80577UG0091ML Data Sheet

Datasheet

15

Deep Sleep state is a very low-power state the processor can enter while maintaining 

context. Deep Sleep state is entered by asserting the DPSLP# pin while in the Sleep 

state. BCLK may be stopped during the Deep Sleep state for additional platform level 

power savings. BCLK stop/restart timings on appropriate chipset based platforms with 

the CK505 clock chip are as follows:

• Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs of 

DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.

• Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels 

within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK 

periods.

To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re-

started after DPSLP# deassertion as described above. A period of 15 microseconds (to 

allow for PLL stabilization) must occur before the processor can be considered to be in 

the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter 

the Stop-Grant state.

While in Deep Sleep state, the processor is incapable of responding to snoop 

transactions or latching interrupt signals. No transitions of signals are allowed on the 

FSB while the processor is in Deep Sleep state. Any transition on an input signal before 

the processor has returned to Stop-Grant state results in unpredictable behavior. 

The Deeper Sleep state is similar to the Deep Sleep state but further reduces core 

voltage levels. One of the potential lower core voltage levels is achieved by entering the 

base Deeper Sleep state. The Deeper Sleep state is entered through assertion of the 

DPRSTP# pin while in the Deep Sleep state. The following lower core voltage level is 

achieved by entering the Intel Enhanced Deeper Sleep state which is a sub-state of 

Deeper Sleep state. Intel Enhanced Deeper Sleep state is entered through assertion of 

the DPRSTP# pin while in the Deep Sleep only when the L2 cache has been completely 

shut down.

Exit from Deeper Sleep is initiated by DPRSTP# deassertion when either core requests 

a core state other than C4 or either core requests a processor performance state other 

than the lowest operating point.

Some processors feature Enhanced Intel SpeedStep Technology. See each processor’s 

DCL to see if it supports Enhanced Intel SpeedStep Technology. Following are the key 

features of Enhanced Intel SpeedStep Technology:

• Multiple voltage and frequency operating points provide optimal performance at the 

lowest power. 

• Voltage and frequency selection is software-controlled by writing to processor 

MSRs:

— If the target frequency is higher than the current frequency, V

CC

 is ramped up 

in steps by placing new values on the VID pins, and the PLL then locks to the 

new frequency.

— If the target frequency is lower than the current frequency, the PLL locks to the 

new frequency and the V

CC

 is changed through the VID pin mechanism.

— Software transitions are accepted at any time. If a previous transition is in 

progress, the new transition is deferred until the previous transition completes.