Intel SU2300 AV80577UG0091ML Data Sheet
Product codes
AV80577UG0091ML
Datasheet
79
Package Mechanical Specifications and Pin Information
LINT[1:0]
Input
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus
agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable
interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR
and NMI are backward compatible with the signals of those names on the Intel®
Pentium® processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC
is enabled by default after Reset, operation of these pins as LINT[1:0] is the default
configuration.
agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable
interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR
and NMI are backward compatible with the signals of those names on the Intel®
Pentium® processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC
is enabled by default after Reset, operation of these pins as LINT[1:0] is the default
configuration.
LOCK#
Input/
Output
LOCK# indicates to the system that a transaction must occur atomically. This signal
must connect the appropriate pins of both FSB agents. For a locked sequence of
transactions, LOCK# is asserted from the beginning of the first transaction to the
end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the FSB, it
waits until it observes LOCK# deasserted. This enables symmetric agents to retain
ownership of the FSB throughout the bus locked operation and ensure the
atomicity of lock.
must connect the appropriate pins of both FSB agents. For a locked sequence of
transactions, LOCK# is asserted from the beginning of the first transaction to the
end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the FSB, it
waits until it observes LOCK# deasserted. This enables symmetric agents to retain
ownership of the FSB throughout the bus locked operation and ensure the
atomicity of lock.
PRDY#
Output
Probe Ready signal used by debug tools to determine processor debug readiness.
PREQ#
Input
Probe Request signal used by debug tools to request debug operation of the
processor.
processor.
PROCHOT#
Input/
Output
As an output, PROCHOT# (Processor Hot) goes active when the processor
temperature monitoring sensor detects that the processor has reached its
maximum safe operating temperature. This indicates that the processor Thermal
Control Circuit (TCC) has been activated, if enabled. As an input, assertion of
PROCHOT# by the system activates the TCC, if enabled. The TCC remains active
until the system deasserts PROCHOT#.
By default PROCHOT# is configured as an output. The processor must be enabled
via the BIOS for PROCHOT# to be configured as bidirectional.
This signal may require voltage translation on the motherboard.
temperature monitoring sensor detects that the processor has reached its
maximum safe operating temperature. This indicates that the processor Thermal
Control Circuit (TCC) has been activated, if enabled. As an input, assertion of
PROCHOT# by the system activates the TCC, if enabled. The TCC remains active
until the system deasserts PROCHOT#.
By default PROCHOT# is configured as an output. The processor must be enabled
via the BIOS for PROCHOT# to be configured as bidirectional.
This signal may require voltage translation on the motherboard.
PSI#
Output
Processor Power Status Indicator signal. This signal is asserted when the processor
is in both in the Normal state (HFM to LFM) and in lower power states (Deep Sleep
and Deeper Sleep).
is in both in the Normal state (HFM to LFM) and in lower power states (Deep Sleep
and Deeper Sleep).
PWRGOOD
Input
PWRGOOD (Power Good) is a processor input. The processor requires this signal to
be a clean indication that the clocks and power supplies are stable and within their
specifications. ‘Clean’ implies that the signal remains low (capable of sinking
leakage current), without glitches, from the time that the power supplies are
turned on until they come within specification. The signal must then transition
monotonically to a high state. PWRGOOD can be driven inactive at any time, but
clocks and power must again be stable before a subsequent rising edge of
PWRGOOD.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
be a clean indication that the clocks and power supplies are stable and within their
specifications. ‘Clean’ implies that the signal remains low (capable of sinking
leakage current), without glitches, from the time that the power supplies are
turned on until they come within specification. The signal must then transition
monotonically to a high state. PWRGOOD can be driven inactive at any time, but
clocks and power must again be stable before a subsequent rising edge of
PWRGOOD.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
REQ[4:0]#
Input/
Output
REQ[4:0]# (Request Command) must connect the appropriate pins of both FSB
agents. They are asserted by the current bus owner to define the currently active
transaction type. These signals are source synchronous to ADSTB[0]#.
agents. They are asserted by the current bus owner to define the currently active
transaction type. These signals are source synchronous to ADSTB[0]#.
Table 22.
Signal Description (Sheet 5 of 7)
Name
Type
Description