Intel LF80550KF0804M Data Sheet

70

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

REQ[4:0]#

I/O

REQ[4:0]# (Request Command) must connect the appropriate pins of all 

processor front side bus agents. They are asserted by the current bus owner to 

define the currently active transaction type. These signals are source 

synchronous to ADSTB[1:0]#. Refer to the AP[1:0]# signal description for 

details on parity checking of these signals.

RESET#

I

Asserting the RESET# signal resets all processors to known states and 

invalidates their internal caches without writing back any of their contents. For 

a power-on Reset, RESET# must stay active for at least 1 ms after V

CC

 and 

BCLK have reached their specified levels. On observing active RESET#, all front 

side bus agents will deassert their outputs within two clocks. RESET# must not 

be kept asserted for more than 10 ms.
A number of bus signals are sampled at the active-to-inactive transition of 

RESET# for power-on configuration. These configuration options are described 

.

RS[2:0]#

I

RS[2:0]# (Response Status) are driven by the response agent (the agent 

responsible for completion of the current transaction), and must connect to the 

appropriate pins of all processor front side bus agents.

RSP#

I

RSP# (Response Parity) is driven by the response agent (the agent responsible 

for completion of the current transaction) during assertion of RS[2:0]#, the 

signals for which RSP# provides parity protection. It must connect to the 

appropriate pins of all processor front side bus agents.
A correct parity signal is electrically high if an even number of covered signals 

are electrically low and electrically low if an odd number of covered signals are 

electrically low. If RS[2:0]# are all electrically high, RSP# is also electrically 

high, since this indicates it is not being driven by any agent guaranteeing 

correct parity.

SKTOCC#

O

SKTOCC# (Socket occupied) will be pulled to ground by the processor to 

indicate that the processor is present. There is no connection to the processor 

silicon for this signal.

SM_ALERT#

O

SM_ALERT# (SMBus Alert) is an asynchronous interrupt line associated with 

the SMBus Thermal Sensor device. It is an open-drain output and the 

processor includes a 10kΩ pull-up resistor to SM_VCC for this signal. For more 

information on the usage of the SM_ALERT# pin, see 

.

SM_CLK

I/O

The SM_CLK (SMBus Clock) signal is an input clock to the system management 

logic which is required for operation of the system management features of the 

Dual-Core Intel Xeon processor 7100 series. This clock is driven by the SMBus 

controller and is asynchronous to other clocks in the processor.The processor 

includes a 10 kΩ pull-up resistor to SM_VCC for this signal.

SM_DAT

I/O

The SM_DAT (SMBus Data) signal is the data signal for the SMBus. This signal 

provides the single-bit mechanism for transferring data between SMBus 

devices. The processor includes a 10 kΩ pull-up resistor to SM_VCC for this 

signal.

SM_EP_A[2:0]

I

The SM_EP_A (EEPROM Select Address) pins are decoded on the SMBus in 

conjunction with the upper address bits in order to maintain unique addresses 

on the SMBus in a system with multiple processors. To set an SM_EP_A line 

high, a pull-up resistor should be used that is no larger than 1 kΩ

.

 The 

processor includes a 10 kΩ pull-down resistor to V

SS

 for each of these signals.

For more information on the usage of these pins, see 

SM_TS_A[1:0]

I

The SM_TS_A (Thermal Sensor Select Address) pins are decoded on the SMBus 

in conjunction with the upper address bits in order to maintain unique 

addresses on the SMBus in a system with multiple processors.
The device’s addressing, as implemented, includes a Hi-Z state for both 

address pins. The use of the Hi-Z state is achieved by leaving the input floating 

(unconnected).
For more information on the usage of these pins, see 

SM_VCC

I

SM_VCC provides power to the SMBus components on the Dual-Core Intel 

Xeon processor 7100 series package.

SM_WP

I

WP (Write Protect) can be used to write protect the Scratch EEPROM. The 

Scratch EEPROM is write-protected when this input is pulled high to SM_VCC. 

The processor includes a 10 kΩ pull-down resistor to V

SS

 for this signal.