Intel 2 Duo T9400 AV80576GH0616M User Manual

Datasheet

33

NOTES:
1.

Each processor is programmed with a maximum valid voltage identification value (VID), which is set at 
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing 
such that two processors at the same frequency may have different settings within the VID range. Note 
that this differs from the VID employed by the processor during a power management event (Intel Thermal 
Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt State). 

2.

The voltage specifications are assumed to be measured across V

CC_SENSE

 and V

SS_SENSE

 pins at socket with 

a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance. 
The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from 
the system is not coupled in the scope probe. 

3.

Specified at 105 °C T

J

. 

4.

Specified at the nominal V

CC

.

5.

Measured at the bulk capacitors on the motherboard.

6.

V

CC,BOOT

 tolerance shown in 

7.

Based on simulations and averaged over the duration of any change in current. Specified by design/
characterization at nominal V

CC

. Not 100% tested.

8.

This is a power-up peak current specification, which is applicable when V

CCP

 is high and V

CC_CORE

 is low.

9.

This is a steady-state I

CC

 current specification, which is applicable when both V

CCP

 and V

CC_CORE

 are high.

10.

The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor will be lesser than or 
equal to 300 mV.

11.

The I

CCDES

 (max) specification of 60 A is for Intel® Core

™

2 Extreme processors only. 

I

AH,

I

SGNT

I

CC

 Auto-Halt & Stop-Grant

HFM
SuperLFM

—

—

29.7
16.7

A

3,  4,  10

I

SLP

I

CC

 Sleep

HFM
SuperLFM

—

—

28.8
16.5

A

3,  4,  10

I

DSLP

I

CC

 Deep Sleep

HFM
SuperLFM

—

—

26.8
16.0

A

3,  4,  10

I

DPRSLP

I

CC

 Deeper Sleep (C4) 

—

—

12.2

A

3, 4

I

DC4

I

CC

 Intel Enhanced Deeper Sleep State 

—

—

11.7

A

3, 4

I

PPWDN

I

CC

 Deep Power Down Technology State (C6) 

—

—

11.0

A

3, 4

dI

CC/

DT

V

CC 

Power Supply Current Slew Rate at 

Processor Package Pin

—

—

600

mA/µs

5, 7

I

CCA

I

CC

 for V

CCA 

Supply

—

—

130

mA

I

CCP

I

CC

 for V

CCP 

Supply before V

CC

 Stable

I

CC

 for V

CCP 

Supply after V

CC

 Stable

—

—

4.5
2.5

A
A

8
9