Intel E5507 AT80602000795AA User Manual

86

Intel

®

 Xeon

®

 Processor 5500 Series Datasheet, Volume 1

DDR_THERM#

I

DDR_THERM# is used for imposing duty cycle throttling on all memory channels. 

The platform should ensure that DDR_THERM# is exerted when any DIMM is 

over T64 (85 °C)

DDR{0/1/2}_BA[2:0]

O

Defines the bank which is the destination for the current Activate, Read, Write, 

or Precharge command.

1

DDR{0/1/2}_CAS#

O

Column Address Strobe. 

DDR{0/1/2}_CKE[3:0]

O

Clock Enable.

DDR{0/1/2}_CLK_N[3:0]
DDR{0/1/2}_CLK_P[3:0]

O

Differential clocks to the DIMM. All command and control signals are valid on the 

rising edge of clock.

DDR{0/1/2}_CS[7:0]#

O

Each signal selects one rank as the target of the command and address.

DDR{0/1/2}_DQ[63:0]

I/O

DDR3 Data bits.

DDR{0/1/2}_DQS_N[17:0]
DDR{0/1/2}_DQS_P[17:0]

I/O

Differential pair, Data/ECC Strobe. Differential strobes latch data/ECC for each 

DRAM. Different numbers of strobes are used depending on whether the 

connected DRAMs are x4,x8. Driven with edges in center of data, receive edges 

are aligned with data edges. 

DDR{0/1/2}_ECC[7:0]

I/O

Check Bits - An Error Correction Code is driven along with data on these lines for 

DIMMs that support that capability. 

DDR{0/1/2}_MA[15:0]

O

Selects the Row address for Reads and writes, and the column address for 

activates. Also used to set values for DRAM configuration registers.

DDR{0/1/2}_MA_PAR

O

Odd parity across Address and Command.

DDR{0/1/2}_ODT[3:0]

O

Enables various combinations of termination resistance in the target and non-

target DIMMs when data is read or written

DDR{0/1/

2}_PAR_ERR#[2:0]

I

Parity Error detected by Registered DIMM (one for each DIMM).

DDR{0/1/2}_RAS#

O

Row Address Strobe.

DDR{0/1/2}_RESET#

O

Resets DRAMs. Held low on power up, held high during self refresh, otherwise 

controlled by configuration register.

DDR_VREF

I

Voltage reference for DDR3.

DDR{0/1/2}_WE#

O

Write Enable.

GTLREF

I

Voltage reference for GTL signals.

ISENSE

I

Current sense for VRD11.1.

PECI

I/O

PECI (Platform Environment Control Interface) is the serial sideband interface to 

the processor and is used primarily for thermal, power and error management. 

PECI_ID#

I

PECI_ID# is the PECI client address identifier. Assertion of this pin results in a 

PECI client address of 0x31 (versus the default 0x30 client address). This pin is 

primarily useful for PECI client address differentiation in DP platforms. One of 

the two processors must be pulled down to VSS to strap to the address of 0x31.

PRDY#

O

PRDY# is a processor output used by debug tools to determine processor debug 

readiness.

PREQ#

I/O

PREQ# is used by debug tools to request debug operation of the processor.

PROCHOT#

I/O

PROCHOT# will go active when the processor temperature monitoring sensor 

detects that the processor has reached its maximum safe operating 

temperature. This indicates that the processor Thermal Control Circuit has been 

activated, if enabled. This signal can also be driven to the processor to activate 

the Thermal Control Circuit. 
If PROCHOT# is asserted at the deassertion of RESET#, the processor will tri-

state its outputs. This signal does not have on-die termination and must be 

terminated on the system board.