Intel E5240 EU80573KJ0806M Data Sheet

89

PECI offers an interface for thermal monitoring of Intel processor and chipset 
components. It uses a single wire, thus alleviating routing congestion issues. 

 shows an example of the PECI topology in a system with Dual-Core Intel® 

Xeon® Processor 5200 Series. PECI uses CRC checking on the host side to ensure 
reliable transfers between the host and client devices. Also, data transfer speeds across 
the PECI interface are negotiable within a wide range (2Kbps to 2Mbps). The PECI 
interface on the Dual-Core Intel® Xeon® Processor 5200 Series is disabled by default 
and must be enabled through BIOS.

Fan speed control solutions based on PECI utilize a T

CONTROL

 value stored in the 

processor IA32_TEMPERATURE_TARGET MSR. The T

CONTROL

 MSR uses the same offset 

temperature format as PECI though it contains no sign bit. Thermal management 
devices should infer the T

CONTROL

 value as negative. Thermal management algorithms 

should utilize the relative temperature value delivered over PECI in conjunction with the 
T

CONTROL

 MSR value to control or optimize fan speeds. 

 shows a conceptual 

fan control diagram using PECI temperatures. 

The relative temperature value reported over PECI represents the data below the onset 
of thermal control circuit (TCC) activation as needed by PROCHOT# assertions. As the 
temperature approaches TCC activation, the PECI value approaches zero. TCC activates 
at a PECI count of zero.