Intel X3210 HH80562QH0468M Data Sheet
Product codes
HH80562QH0468M
6
Dual-Core Intel® Xeon® Processor 3000 Series Datasheet
Tables
Voltage Identification Definition ...............................................................................17
1, 2, 3, 4
.......................................18
Absolute Maximum and Minimum Ratings..................................................................20
CC
Static and Transient Tolerance for Processors with 4 MB L2 Cache ..........................21
CC
Static and Transient Tolerance for Processors with 2 MB L2 Cache ..........................22
CC
Overshoot Specifications...................................................................................24
Signal Characteristics .............................................................................................26
2-10 Signal Reference Voltages.......................................................................................26
2-11 GTL+ Signal Group DC Specifications .......................................................................27
2-12 Open Drain and TAP Output Signal Group DC Specifications.........................................27
2-13 CMOS Signal Group DC Specifications.......................................................................28
2-14 PECI DC Electrical Limits.........................................................................................28
2-15 GTL+ Bus Voltage Definitions ..................................................................................29
2-16 Core Frequency to FSB Multiplier Configuration ..........................................................30
2-17 BSEL[2:0] Frequency Table for BCLK[1:0].................................................................30
2-18 Front Side Bus Differential BCLK Specifications ..........................................................31
2-19 Front Side Bus Differential BCLK Specifications ..........................................................32
20
2-11 GTL+ Signal Group DC Specifications .......................................................................27
2-12 Open Drain and TAP Output Signal Group DC Specifications.........................................27
2-13 CMOS Signal Group DC Specifications.......................................................................28
2-14 PECI DC Electrical Limits.........................................................................................28
2-15 GTL+ Bus Voltage Definitions ..................................................................................29
2-16 Core Frequency to FSB Multiplier Configuration ..........................................................30
2-17 BSEL[2:0] Frequency Table for BCLK[1:0].................................................................30
2-18 Front Side Bus Differential BCLK Specifications ..........................................................31
2-19 Front Side Bus Differential BCLK Specifications ..........................................................32
20