Intel QX9775 EU80574XL088N Data Sheet

10

The processor is intended for high performance server and workstation systems. The 

processor supports a Dual Independent Bus (DIB) architecture with one processor on 

each bus, up to two processor sockets in a system. The DIB architecture provides 

improved performance by allowing increased FSB speeds and bandwidth. The processor 

is packaged in an FC-LGA Land Grid Array package with 771 lands for improved power 

delivery. It uses a surface mount LGA771 socket that supports Direct Socket Loading 

(DSL).

The Intel

®

 Core™2 Extreme processor QX9775-based platforms implement 

independent core voltage (V

CC

) power planes for each processor. FSB termination 

voltage (V

TT

) is shared and must connect to all FSB agents. The processor core voltage 

uses power delivery guidelines specified by VRM/EVRD 11.0 and its associated load line 

(see Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 

11.0 Design Guidelines for further details). VRM/EVRD 11.0 will support the power 

requirements of all frequencies of the processor. 

The processor supports a1600 MHz Front Side Bus operations. The FSB uses a split-

transaction, deferred reply protocol and Source-Synchronous Transfer (SST) of address 

and data to improve performance. The processor transfers data four times per bus 

clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address 

bus can deliver addresses two times per bus clock and is referred to as a ‘double-

clocked’ or a 2X address bus. In addition, the Request Phase completes in one clock 

cycle. The FSB is also used to deliver interrupts.

Signals on the FSB use Assisted Gunning Transceiver Logic (AGTL+) level voltages. 

 contains the electrical specifications of the FSB.

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in 

the asserted state when driven to a low level. For example, when RESET# is low, a 

reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has 

occurred. In the case of signals where the name does not imply an active state but 

describes part of a binary sequence (such as address or data), the ‘#’ symbol implies 

that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and 

D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

Commonly used terms are explained here for clarification:

• Intel

®

 Core™2 Extreme processor QX9775 – Intel

®

 64-bit microprocessor intended 

for dual processor desktops. The processor is based on Intel’s 45 nanometer 

process, and packaged in the FC-LGA package with four processor cores. 

• FC-LGA (Flip Chip Land Grid Array) Package – The processor package is a Land 

Grid Array, consisting of a processor core mounted on a pinless substrate with 771 

lands, and includes an integrated heat spreader (IHS).

• LGA771 socket – The processor interfaces to the baseboard through this surface 

mount, 771 Land socket. See the LGA771 Socket Design Guidelines for details 

regarding this socket.

• Processor core – Processor core with integrated L1 cache. L2 cache and system 

bus interface are shared between the two cores on the die. All AC timing and signal 

integrity specifications are at the pads of the system bus interface.

• Front Side Bus (FSB) – The electrical interface that connects the processor to the 

chipset. Also referred to as the processor system bus or the system bus. All 

memory and I/O transactions, as well as interrupt messages, pass between the 

processor and chipset over the FSB.

• Dual Independent Bus (DIB) – A front side bus architecture with one processor 

on each of several processor buses, rather than a processor bus shared between