Intel QX9775 EU80574XL088N Data Sheet

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Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# utilize 

CMOS input buffers. Legacy output signals such as FERR#/PBE#, IERR#, PROCHOT#, 

and THERMTRIP# utilize open drain output buffers. All of the CMOS and Open Drain 

signals are required to be asserted/deasserted for at least eight BCLKs in order for the 

processor to recognize the proper signal state. See 

 for the DC 

specifications. See 

 for additional timing requirements for entering and 

leaving the low power states.

Due to the voltage levels supported by other components in the Test Access Port (TAP) 

logic, it is recommended that the processor(s) be first in the TAP chain followed by any 

other components within the system. A translation buffer should be used to connect to 

the rest of the chain unless one of the other components is capable of accepting an 

input of the appropriate voltage. Similar considerations must be made for TCK, TDO, 

TMS, and TRST#. Two copies of each signal may be required with each driving a 

different voltage level. 

PECI is an Intel proprietary one-wire interface that provides a communication channel 

between Intel processors and chipset components to external thermal monitoring 

devices. The processor contains Digital Thermal Sensor (DTS) sprinkled both inside and 

outside the cores in a die. These sensors are implemented as analog-to-digital 

converters calibrated at the factory for reasonable accuracy to provide a digital 

representation of relative processor temperature. PECI provides an interface to relay 

the highest DTS temperature within a die to external devices for thermal/fan speed 

control. More detailed information may be found in the Platform Environment Control 

The PECI interface operates at a nominal voltage set by V

TT

. The set of DC electrical 

specifications shown in 

 is used with devices normally operating from a V

TT

 

interface supply. V

TT

 nominal levels will vary between processor families. All PECI 

devices will operate at the V

TT

 level determined by the processor installed in the 

system. For specific nominal V

TT

 levels, refer to 

.

A[37:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, 
BINIT#, BNR#, BPM[5:0]#, 
BPMb[3:0]#,BPRI#, BR[1:0]#, D[63:0]#, 
DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, 
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, 
FORCEPR#, HIT#, HITM#, LOCK#, MCERR#, 
RESET#, REQ[4:0]#, RS[2:0]#, RSP#, 
TRDY#

A20M#, LINT0/INTR, LINT1/NMI, IGNNE#, 
INIT#, PWRGOOD, SMI#, STPCLK#, TCK, TDI, 
TMS, TRST#