Intel QX9775 EU80574XL088N Data Sheet

26

NOTES:
1.

Unless otherwise noted, all specifications in this table are based on final silicon 
characterization data.

2.

These voltages are targets only. A variable voltage source should exist on systems in the 
event that a different voltage is required. See 

 for more information. 

3.

The voltage specification requirements are measured across the VCC_DIE_SENSE and 
VSS_DIE_SENSE lands and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands 
with an oscilloscope set to 100 MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 
MΩ minimum impedance. The maximum length of ground wire on the probe should be less 

than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 

4.

The processor must not be subjected to any static V

CC

 level that exceeds the V

CC_MAX

 

associated with any particular current. Failure to adhere to this specification can shorten 
processor lifetime.

5.

I

CC_MAX

 specification is based on maximum V

CC 

loadline. Refer to 

 for details. 

The processor is capable of drawing I

CC_MAX 

for up to 10 ms. Refer to 

 for further 

details on the average processor current draw over various time durations.

6.

This specification represents the total current for.

7.

V

TT

 must be provided via a separate voltage source and must not be connected to V

CC

. 

This specification is measured at the land.

VID

VID range

0.850

—

1.3500

V

V

CC

Processor Number:
QX9775

V

CC

 for processor core

3.2 GHz

See 

 and 

V

2, 3, 4, 8, 

18

V

cc_boot

Default VCC Voltage for initial power up

—

1.10

—

V

2

V

VID_STEP

VID step size during a transition

—

—

± 12.5

mV

V

VID_SHIFT

Total allowable DC load line shift from VID steps

—

—

450

mV

9

V

TT

FSB termination voltage (DC + AC specification)

1.045

1.10

1.155

V

7,12

V

CCPLL

PLL supply voltage (DC + AC specification)

1.455

1.500

1.605

V

11

I

CC

Processor Number:

QX9775

I

CC

 processor core with 

multiple VID” 
3.2 GHz

—

—

150

A

4,5,8,17, 

18

I

CC_RESET

Processor Number:

QX9775

I

CC_RESET

 core with 

multiple VID:
3.2 GHz

—

—

150

A

16,17

I

TT

I

CC

 for V

TT

 supply before V

CC

 stable

I

CC

 for V

TT

 supply after V

CC

 stable

—

—

8

7

A

14

I

CC_TDC

Processor Number:

QX9775

Thermal Design Current 
(TDC): 
3.2 GHz

—

—

130

A

13,17,18

I

CC_VTT_OUT

DC current that may be drawn from V

TT_OUT 

per 

land 

—

—

580

mA

15

I

CC_GTLREF

I

CC

 for 

GTLREF_DATA_MID, GTLREF_DATA_END, 
GTLREF_ADD_MID, and GTLREF_ADD_END

—

—

200

µA

6

I

CC_VCCPLL

I

CC

 for PLL supply

—

—

260

mA

11

I

TCC

I

CC 

during active thermal control circuit (TCC)

—

—

150

A

17