Intel QX9775 EU80574XL088N Data Sheet

64

A[37:3]#

I/O

A[37:3]# (Address) define a 2

38

-byte physical memory 

address space. In sub-phase 1 of the address phase, 
these signals transmit the address of a transaction. In 
sub-phase 2, these signals transmit transaction type 
information. These signals must connect the appropriate 
pins of all agents on the FSB. A[37:3]# are protected by 
parity signals AP[1:0]#. A[37:3]# are source 
synchronous signals and are latched into the receiving 
buffers by ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the 
processors sample a subset of the A[37:3]# lands to 
determine their power-on configuration. See 

3

A20M#

I

If A20M# (Address-20 Mask) is asserted, the processor 
masks physical address bit 20 (A20#) before looking up a 
line in any internal cache and before driving a read/write 
transaction on the bus. Asserting A20M# emulates the 
8086 processor's address wrap-around at the 1 MB 
boundary. Assertion of A20M# is only supported in real 
mode.
A20M# is an asynchronous signal. However, to ensure 
recognition of this signal following an I/O write 
instruction, it must be valid along with the TRDY# 
assertion of the corresponding I/O write bus transaction. 

2

ADS#

I/O

ADS# (Address Strobe) is asserted to indicate the validity 
of the transaction address on the A[37:3]# lands. All bus 
agents observe the ADS# activation to begin parity 
checking, protocol checking, address decode, internal 
snoop, or deferred reply ID match operations associated 
with the new transaction. This signal must be connected 
to the appropriate pins on all processor FSB agents.

3

ADSTB[1:0]#

I/O

Address strobes are used to latch A[37:3]# and 
REQ[4:0]# on their rising and falling edge. Strobes are 
associated with signals as shown below.

3

REQ[4:0]#, 

A[16:3]#, A[37:36]#

ADSTB0#

A[35:17]#

ADSTB1#