Intel QX9775 EU80574XL088N Data Sheet

87

The system can generate a STPCLK# while the processor is in the HALT state. When the 

system deasserts STPCLK#, the processor will return execution to the HALT state.

While in HALT state, the processor will process front side bus snoops and interrupts.

Extended HALT state is a low power state entered when all processor cores have 

executed the HALT or MWAIT instructions and Extended HALT state has been enabled 

via the BIOS. When one of the processor cores executes the HALT instruction, that 

processor core is halted; however, the other processor core continues normal 

operation. The Extended HALT state is a lower power state than the HALT state or Stop 

Grant state. The Extended HALT state must be enabled for the processor to remain 

within its specifications. 

The processor will automatically transition to a lower core frequency and voltage 

operating point before entering the Extended HALT state. Note that the processor FSB 

frequency is not altered; only the internal core frequency is changed. When entering 

the low power state, the processor will first switch to the lower bus to core frequency 

ratio and then transition to the lower voltage (VID). 

While in the Extended HALT state, the processor will process bus snoops.

NOTE:
1.

The specification is at Tcase = 40 °C and nominal Vcc. The VID setting represents the 
maximum expected VID when running in HALT state.

2.

Processors running in the lowest bus ratio supported as shown in 

, will enter the 

HALT State when the processor has executed the HALT or MWAIT instruction since the 
processor is already operating in the lowest core frequency and voltage operating point.

The processor exits the Extended HALT state when a break event occurs. When the 

processor exits the Extended HALT state, it will first transition the VID to the original 

value and then change the bus to core frequency ratio back to the original value.

When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered no 

later than 20 bus clocks after the response phase of the processor issued Stop Grant 

Acknowledge special bus cycle. By default, the processor will issue two Stop Grant 

Acknowledge special bus cycles, one for each die. Once the STPCLK# pin has been 

asserted, it may only be deasserted once the processor is in the Stop Grant state. All 

processor cores will enter the Stop-Grant state once the STPCLK# pin is asserted. 

Additionally, all processor cores must be in the Stop Grant state before the de-assertion 

of STPCLK#.

Since the AGTL+ signal pins receive power from the front side bus, these pins should 

not be driven (allowing the level to return to V

TT

) for minimum power drawn by the 

termination resistors in this state. In addition, all other input pins on the front side bus 

should be driven to the inactive state.

BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be 

latched and can be serviced by software upon exit from the Stop Grant state.

P

EXTENDED_HALT

Extended HALT 

State Power

—

—

16

W

1,2