Intel E7320 LF80565QH0464M Data Sheet
Product codes
LF80565QH0464M
Introduction
10
Document Number: 318080-002
The Intel
®
Xeon
®
Processor 7200 Series and 7300 Series support Intel
®
Virtualization
Technology for hardware-assisted virtualization within the processor. Intel
Virtualization Technology is a set of hardware enhancements that can improve
virtualization solutions. Intel Virtualization Technology is used in conjunction with
Virtual Machine Monitor software enabling multiple, independent software
environments inside a single platform. Further details on Intel Virtualization Technology
can be found at
Virtualization Technology is a set of hardware enhancements that can improve
virtualization solutions. Intel Virtualization Technology is used in conjunction with
Virtual Machine Monitor software enabling multiple, independent software
environments inside a single platform. Further details on Intel Virtualization Technology
can be found at
http://developer.intel.com/technology/vt
.
The Intel
®
Xeon
®
Processor 7200 Series and 7300 Series are intended for high
performance multi-processor server systems. The processors support a Multi
Independent Bus (MIB) architecture with one processor on each bus. The MIB
architecture provides improved performance by allowing increased FSB speeds and
bandwidth. All versions of the Intel
Independent Bus (MIB) architecture with one processor on each bus. The MIB
architecture provides improved performance by allowing increased FSB speeds and
bandwidth. All versions of the Intel
®
Xeon
®
Processor 7200 Series and 7300 Series will
include manageability features. Components of the manageability features include an
OEM EEPROM and Processor Information ROM which are accessed through an SMBus
interface and contain information relevant to the particular processor and system in
which it is installed. The Intel
OEM EEPROM and Processor Information ROM which are accessed through an SMBus
interface and contain information relevant to the particular processor and system in
which it is installed. The Intel
®
Xeon
®
Processor 7200 Series and 7300 Series is
packaged in a 604-pin Flip Chip Micro Pin Grid Array (FC-mPGA6) package and utilizes
a surface-mount Zero Insertion Force (ZIF) mPGA604 socket. The Intel
a surface-mount Zero Insertion Force (ZIF) mPGA604 socket. The Intel
®
Xeon
®
Processor 7200 Series and 7300 Series support 40-bit addressing.
Intel
®
Xeon
®
Processor 7200 Series and 7300 Series-based platforms implement
independent core voltage (V
CC
) power planes for each processor. FSB termination
voltage (V
TT
) is shared and must connect to all FSB agents. The processor core voltage
utilizes power delivery guidelines specified by VRM/EVRD 11.0 and its associated load
line (see Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down
(EVRD) 11.0 Design Guidelines for further details). VRM/EVRD 11.0 will support the
power requirements of all frequencies of the processors including Flexible Motherboard
Guidelines (FMB) (see
line (see Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down
(EVRD) 11.0 Design Guidelines for further details). VRM/EVRD 11.0 will support the
power requirements of all frequencies of the processors including Flexible Motherboard
Guidelines (FMB) (see
). Refer to the appropriate platform design
guidelines for implementation details.
The Intel
®
Xeon
®
Processor 7200 Series and 7300 Series supports 1066 MHz Front
Side Bus operation. The FSB utilizes a split-transaction, deferred reply protocol and
Source-Synchronous Transfer (SST) of address and data to improve performance. The
processor transfers data four times per bus clock (4X data transfer rate, as in AGP 4X).
Along with the 4X data bus, the address bus can deliver addresses two times per bus
clock and is referred to as a ‘double-clocked’ or a 2X address bus. In addition, the
Request Phase completes in one clock cycle. Working together, the 4X data bus and 2X
address bus provide a data bus bandwidth of up to 8.5 GBytes per second. The FSB is
also used to deliver interrupts.
Source-Synchronous Transfer (SST) of address and data to improve performance. The
processor transfers data four times per bus clock (4X data transfer rate, as in AGP 4X).
Along with the 4X data bus, the address bus can deliver addresses two times per bus
clock and is referred to as a ‘double-clocked’ or a 2X address bus. In addition, the
Request Phase completes in one clock cycle. Working together, the 4X data bus and 2X
address bus provide a data bus bandwidth of up to 8.5 GBytes per second. The FSB is
also used to deliver interrupts.
Table 1-1.
Quad-Core Intel® Xeon® Processor 7300 Series Processor Features
# of Processor
Cores
L1 Cache per core
L2 Advanced
Transfer Cache
Front Side Bus
Frequency
Package
4
32 KB instruction
32 KB data
4M Shared L2
Cache per die
8M Total Cache
1066 MHz
FC-mPGA6
Table 1-2.
Dual-Core Intel® Xeon® Processor 7200 Series Processor Features
# of Processor
Cores
L1 Cache per core
L2 Advanced
Transfer Cache
Front Side Bus
Frequency
Package
2
32 KB instruction
32 KB data
4M L2 Cache per die
8M Total Cache
1066 MHz
FC-mPGA6