Intel E7320 LF80565QH0464M Data Sheet

Document Number: 318080-002

21

1.

Refer to 

 for signal descriptions.

2.

These signals may be driven simultaneously by multiple agents (Wired-OR).

AGTL+ Common Clock Input

Synchronous to BCLK[1:0]

BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, 

TRDY#;

AGTL+ Common Clock Output

Synchronous to BCLK[1:0]

BPM4#, BPM[2:1]#, BPMb[2:1]#

AGTL+ Common Clock I/O

Synchronous to BCLK[1:0]

ADS#, AP[1:0]#, BINIT#

2

, BNR#

2

, BPM5#, 

BPM3#, BPM0#, BPMb3#, BPMb0#, 

BR[1:0]#, DBSY#, DP[3:0]#, DRDY#, HIT#

2

, 

HITM#

2

, LOCK#, MCERR#

2

AGTL+ Source Synchronous 

I/O

Synchronous to assoc. 

strobe

AGTL+ Strobes I/O

Synchronous to BCLK[1:0]

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

Open Drain Output

Asynchronous

FERR#/PBE#, IERR#, PROCHOT#, 

THERMTRIP#, TDO

CMOS Asynchronous Input 

Asynchronous

A20M#, FORCEPR#, IGNNE#, INIT#, 

LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, 

STPCLK#, TCK, TDI, TMS TRST#

CMOS Asynchronous Output 

Asynchronous

BSEL[2:0], VID[6:1]

FSB Clock

Clock

BCLK[1:0]

SMBus

Synchronous to SM_CLK

SM_CLK, SM_DAT, SM_EP_A[2:0], SM_WP

Power/Other

Power/Other

COMP[3:0], GTLREF_ADD_MID, 

GTLREF_ADD_END, GTLREF_DATA_MID, 

GTLREF_DATA_END, LL_ID[1:0], 

PROC_ID[1:0], PECI, RESERVED, 

SKTOCC#,SM_VCC, TESTHI[1:0], TESTIN1, 

TESTIN2, VCC, VCC_SENSE, VCC_SENSE2, 

VCCPLL, VSS_SENSE, VSS_SENSE2, VSS, 

VTT, VTT_SEL

REQ[4:0]# 

A[37:36,16:3]#

ADSTB0#

A[39:38, 35:17]#

ADSTB1#

D[15:0]#, DBI0# 

DSTBP0#, DSTBN0#

D[31:16]#, DBI1# 

DSTBP1#, DSTBN1#

D[47:32]#, DBI2# 

DSTBP2#, DSTBN2#

D[63:48]#, DBI3# 

DSTBP3#, DSTBN3#