Intel E7320 LF80565QH0464M Data Sheet
Product codes
LF80565QH0464M
Document Number: 318080-002
5
Figures
®
Xeon
®
Processor 7200 Series and 7300 Series Load Current versus
Time28
Quad-Core Intel® Xeon® X7350 Processor Load Current versus Time ................. 29
®
Xeon
®
Processor 7200 Series and 7300 Series VCC Static and Transient
Tolerance Load Lines ......................................................................................... 31
Quad-Core Intel® Xeon® X7350 Processor VCC Static and Transient Tolerance
Load Lines........................................................................................................ 32
Load Lines........................................................................................................ 32
Static and Transient Tolerance
Load Lines........................................................................................................ 33
2-10 VCC Overshoot Example Waveform...................................................................... 38
2-11 Electrical Test Circuit ......................................................................................... 46
2-12 TCK Clock Waveform ......................................................................................... 46
2-13 Differential Clock Waveform................................................................................ 47
2-14 Differential Clock Crosspoint Specification............................................................. 47
2-15 BCLK Waveform at Processor Pad and Pin ............................................................. 48
2-16 FSB Common Clock Valid Delay Timing Waveform ................................................. 48
2-17 FSB Source Synchronous 2X (Address) Timing Waveform ....................................... 49
2-18 FSB Source Synchronous 4X (Data) Timing Waveform............................................ 50
2-19 TAP Valid Delay Timing Waveform ....................................................................... 51
2-20 Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform............... 51
2-21 THERMTRIP# Power Down Sequence ................................................................... 51
2-22 SMBus Timing Waveform.................................................................................... 52
2-23 SMBus Valid Delay Timing Waveform ................................................................... 52
2-24 Voltage Sequence Timing Requirements ............................................................... 53
2-25 FERR#/PBE# Valid Delay Timing ......................................................................... 54
2-26 VID Step Timings .............................................................................................. 54
2-27 VID Step Times and Vcc Waveforms .................................................................... 55
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2-11 Electrical Test Circuit ......................................................................................... 46
2-12 TCK Clock Waveform ......................................................................................... 46
2-13 Differential Clock Waveform................................................................................ 47
2-14 Differential Clock Crosspoint Specification............................................................. 47
2-15 BCLK Waveform at Processor Pad and Pin ............................................................. 48
2-16 FSB Common Clock Valid Delay Timing Waveform ................................................. 48
2-17 FSB Source Synchronous 2X (Address) Timing Waveform ....................................... 49
2-18 FSB Source Synchronous 4X (Data) Timing Waveform............................................ 50
2-19 TAP Valid Delay Timing Waveform ....................................................................... 51
2-20 Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform............... 51
2-21 THERMTRIP# Power Down Sequence ................................................................... 51
2-22 SMBus Timing Waveform.................................................................................... 52
2-23 SMBus Valid Delay Timing Waveform ................................................................... 52
2-24 Voltage Sequence Timing Requirements ............................................................... 53
2-25 FERR#/PBE# Valid Delay Timing ......................................................................... 54
2-26 VID Step Timings .............................................................................................. 54
2-27 VID Step Times and Vcc Waveforms .................................................................... 55
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