Intel Core™2 Extreme Processor QX6800 (8M Cache, 2.93 GHz, 1066 MHz FSB) HH80562XH0778M Data Sheet

18

Datasheet

1.

Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data.

These specifications will be updated with characterized data from silicon measurements at a later date.

2.

Adherence to the voltage specifications for the processor are required to ensure reliable processor operation.

VID Range

VID

0.8500

—

1.5

V

3

3.

Each processor is programmed with a maximum valid voltage identification value (VID), which is set at

manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing such

that two processors at the same frequency may have different settings within the VID range. Note this differs

from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel

SpeedStep

®

 Technology, or Extended HALT State). 

V

CC

Processor number

QX6800

2.93 GHz

Refer to 

 and 

V

4, 5, 6

4.

These voltages are targets only. A variable voltage source should exist on systems in the event that a different

voltage is required. See 

 and 

 for more information.

5.

The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket

with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance.

The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the

system is not coupled into the oscilloscope probe.

6.

Refer to 

 for the minimum, typical, and maximum V

CC

 allowed for a given current. The

processor should not be subjected to any V

CC

 and I

CC

 combination wherein V

CC

 exceeds V

CC_MAX

 for a given

current.

V

CC_BOOT

Default V

CC

 voltage for initial power up

—

1.10

—

V

V

CCPLL

PLL V

CC

- 5%

1.50

+ 5%

I

CC

Processor number

QX6800

2.93 GHz

—

—

155

A

7

7.

I

CC_MAX

 specification is based on the V

CC_MAX 

loadline. Refer to 

 for details.

I

TCC

I

CC

 TCC active

—

—

I

CC

A

8

8.

The maximum instantaneous current the processor will draw while the thermal control circuit is active (as

indicated by the assertion of PROCHOT#) is the same as the maximum I

CC

 for the processor.

V

TT

FSB termination voltage 
(DC + AC specifications)

1.14

1.20

1.26

V

9, 10

9.

V

TT

 must be provided via a separate voltage source and not be connected to V

CC

. This specification is measured

at the land.

10.

Baseboard bandwidth is limited to 20 MHz.

VTT_OUT_LEFT 
and 
VTT_OUT_RIGHT 
I

CC

DC Current that may be drawn from 
VTT_OUT_LEFT and VTT_OUT_RIGHT per pin

—

—

580

mA

I

TT

I

CC

 for V

TT

 supply before V

CC

 stable

I

CC

 for V

TT

 supply after V

CC

 stable

—

—

8.0
7.0

A

11

11.

This is maximum total current drawn from V

TT

 plane by only the processor. This specification does not include

the current coming from R

TT

 (through the signal line). Refer to the 

 to determine the total I

TT

 drawn by the system. This parameter

is based on design characterization and is not tested.

I

CC_VCCPLL

I

CC

 for PLL land

—

—

130

mA

I

CC_GTLREF

I

CC

 for GTLREF

—

-—

200

μA