Intel AT80604004884AA User Manual
Intel® Xeon® Processor 7500 Datasheet, Volume 1
21
Electrical Specifications
Notes:
1.
When the “11111111” VID pattern is observed, or when the SKTOCC# pin is deasserted, the voltage
regulator output should be disabled.
2.
Shading denotes the expected VID range of the Intel® Xeon® processor 7500 series.
3.
The VID range includes VID transitions that may be initiated by thermal events, Extended HALT state
transitions, higher C-States or Enhanced Intel SpeedStep
®
Technology transitions. The Extended HALT
state must be enabled for the processor to remain within its specifications
4.
Once the VRM/EVRD is operating after power-up, if either the Output Enable signal is de-asserted or a
specific VID off code is received, the VRM/EVRD must turn off its output (the output should go to high
impedance) within 500 ms and latch off until power is cycled. Refer to Voltage Regulator Module (VRM) and
Enterprise Voltage Regulator-Down (EVRD) 11.1 Design Guidelines.
1
0
0
1
0
1
1
1
0.66875
1
0
0
1
1
0
0
0
0.66250
1
0
0
1
1
0
0
1
0.65625
1
0
0
1
1
0
1
0
0.65000
1
0
0
1
1
0
1
1
0.64375
1
0
0
1
1
1
0
0
0.63750
1
0
0
1
1
1
0
1
0.63125
1
0
0
1
1
1
1
0
0.62500
1
0
0
1
1
1
1
1
0.61875
1
0
1
0
0
0
0
0
0.61250
1
0
1
0
0
0
0
1
0.60625
1
0
1
0
0
0
1
0
0.60000
1
0
1
0
0
0
1
1
0.59375
1
0
1
0
0
1
0
0
0.58750
1
0
1
0
0
1
0
1
0.58125
1
0
1
0
0
1
1
0
0.57500
1
0
1
0
0
1
1
1
0.56875
1
0
1
0
1
0
0
0
0.56250
1
0
1
0
1
0
0
1
0.55625
1
0
1
0
1
0
1
0
0.55000
1
0
1
0
1
0
1
1
0.54375
1
0
1
0
1
1
0
0
0.53750
1
0
1
0
1
1
0
1
0.53125
1
0
1
0
1
1
1
0
0.52500
1
0
1
0
1
1
1
1
0.51875
1
0
1
1
0
0
0
0
0.51250
1
0
1
1
0
0
0
1
0.50625
1
0
1
1
0
0
1
0
0.50000
1
1
1
1
1
1
1
0
OFF
1
1
1
1
1
1
1
1
OFF
Table 2-2.
Voltage Identification Definition (Sheet 5 of 5)
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
V
CC_MAX