Intel AT80604004884AA User Manual

30

Intel® Xeon® Processor 7500 Datasheet, Volume 1

1.

The given PLL parameters are: Underdamping (z) = 0.8 and natural frequency = fn = 7.86E6 Hz; w

n

 = 2 * 

fn. N_minUI = 12 for Intel® QPI Phy 1 channel.

Link speed independent specifications call out the transmitter and receiver parameters 
required at all link speeds. The transmitter specifications are for stand-alone, individual 
transmitters (Tx). The validation setup for Tx is called out in 

f

Refclk

System clock frequency

133.33

MHz

ER

Refclk-diffRise,

ER

Refclk-diffFall

Rise and fall slope 

parameter

1.0

4.0

V/nsec

V

Refclk-max

Single ended maximum 

voltage with overshoot

1150

mV

V

Refclk-min

Single ended minimum 

voltage with overshoot

-350

mV

V

Cross

Absolute crossing point 

limits between Refclk+ and 

Refclk- waveforms

250

550

mV

See 

V

Cross_delta

Peak-peak variation in 

crossing points

140

See 

V

Refclk_diff-ih

High of the differential 

voltage (V

Refclk

+ - V

Refclk

-) 

above zero

150

mV

V

Refclk_diff-il

Low of the differential 

voltage (V

Refclk

+ - V

Refclk

-) 

above zero

-150

mV

T

Refclk-Dutycycle

Duty cycle of reference 

clock.

40 50

60

% 

T

Refclk-jitter-rms-onepll

Accumulated rms jitter over 

n UI of a given PLL model 

output in response to the 

jittery reference clock 

input. The PLL output is 

generated by convolving 

the measured reference 

clock phase jitter with a 

given PLL transfer function. 

Here n=12.

 0.5

psec

1

TRefclk-diff-jit

Phase Drift between clocks 

at two connected ports

500

psec

TRefclk-C2C-jit

Short term difference in the 

period of any two adjacent 

clock cycles

100

psec

At via