Intel Xeon LV 5128 HH80556JH0364M Data Sheet
Product codes
HH80556JH0364M
Dual-Core Intel
®
Xeon
®
Processor 5100 Series Datasheet
87
Thermal Specifications
6.3.1.1
Key Difference with Legacy Diode-Based Thermal Management
Fan speed control solutions utilize a TControl value stored in the processor
IA32_TEMPERATURE_TARGET MSR. Prior to Dual-Core Intel
IA32_TEMPERATURE_TARGET MSR. Prior to Dual-Core Intel
®
Xeon
®
Processor 5100
Series , TControl represented a diode temperature. With Dual-Core Intel
®
Xeon
®
Processor 5100 Series , TControl represents an offset from TCC activation
temperature.The DTS outputs temperature offsets over the PECI interface in response
to a GetTemp0() command and these offsets are relative values vs. an absolute values.
The temperature reported over PECI is always a negative value and represents a delta
below the onset of thermal control circuit (TCC) activation, as indicated by PROCHOT#.
Therefore, as the temperature approaches TCC activation, the value approaches zero
degrees Celsius. At zero degrees, the TCC activates as described in
temperature.The DTS outputs temperature offsets over the PECI interface in response
to a GetTemp0() command and these offsets are relative values vs. an absolute values.
The temperature reported over PECI is always a negative value and represents a delta
below the onset of thermal control circuit (TCC) activation, as indicated by PROCHOT#.
Therefore, as the temperature approaches TCC activation, the value approaches zero
degrees Celsius. At zero degrees, the TCC activates as described in
format comparison is shown below in
While the Tcontrol value for PECI based digital temperature data is different than
legacy, it will use the same processor register, and it will still be necessary for thermal
management algorithms to use this new relative temperature format delivered over
PECI to control fans or other temperature control methods.
legacy, it will use the same processor register, and it will still be necessary for thermal
management algorithms to use this new relative temperature format delivered over
PECI to control fans or other temperature control methods.
Figure 6-7. PECI Topology
PECI Host
Controller
Controller
PECI
Processor
(Socket 0)
Processor
(Socket 1)
Addr 0x31
PECI
Pin
G5
Pin
G5
Addr 0x30
For Dual-Core Intel® Xeon® Processor 5100 Series