Intel W3680 AT80613003543AF Data Sheet

34

Dual-Core Intel® Xeon® Processor 3000 Series Datasheet

I

leak-

High impedance leakage to GND 

N/A

10

µA

C

bus

Bus capacitance per node

N/A

10

pF

4

V

noise

Signal noise immunity above 300 MHz

0.1 * V

TT

—

V

p-p

1.

V

TT

 supplies the PECI interface. PECI behavior does not affect V

TT

 min/max specifications. Refer

 for V

TT

 specifications. 

2. The input buffers use a Schmitt-triggered input design for improved noise immunity. 
3. The leakage specification applies to powered devices on the PECI bus.
4. One node is counted for each client and one node for the system host. Extended trace lengths

might appear as additional nodes.