Intel E6540 HH80557PJ0534M User Manual

Product codes

HH80557PJ0534M

Datasheet

Contents

Introduction ............................................................................................................ 11
1.1

Terminology ..................................................................................................... 12
1.1.1

Processor Terminology ............................................................................ 12

1.2

References ....................................................................................................... 14

Electrical Specifications ........................................................................................... 15
2.1

Power and Ground Lands.................................................................................... 15

2.2

Decoupling Guidelines........................................................................................ 15

2.2.1

VCC Decoupling ..................................................................................... 15

2.2.2

Vtt Decoupling ....................................................................................... 15

2.2.3

FSB Decoupling...................................................................................... 16

2.3

Voltage Identification ......................................................................................... 16

2.4

Market Segment Identification (MSID) ................................................................. 18

2.5

Reserved, Unused, and TESTHI Signals ................................................................ 18

2.6

Voltage and Current Specification ........................................................................ 19

2.6.1

Absolute Maximum and Minimum Ratings .................................................. 19

2.6.2

DC Voltage and Current Specification ........................................................ 20

2.6.3

Overshoot ....................................................................................... 25

2.6.4

Die Voltage Validation ............................................................................. 26

2.7

Signaling Specifications...................................................................................... 26

2.7.1

FSB Signal Groups.................................................................................. 27

2.7.2

CMOS and Open Drain Signals ................................................................. 28

2.7.3

Processor DC Specifications ..................................................................... 29

2.7.3.1

GTL+ Front Side Bus Specifications ............................................. 30

2.7.4

Clock Specifications ................................................................................ 31

2.7.5

Front Side Bus Clock (BCLK[1:0]) and Processor Clocking ............................ 31

2.7.6

FSB Frequency Select Signals (BSEL[2:0])................................................. 31

2.7.7

Phase Lock Loop (PLL) and Filter .............................................................. 32

2.7.8

BCLK[1:0] Specifications (CK505 based Platforms) ..................................... 32

2.7.9

BCLK[1:0] Specifications (CK410 based Platforms) ..................................... 34

2.8

PECI DC Specifications ....................................................................................... 35

Package Mechanical Specifications .......................................................................... 37
3.1

Package Mechanical Drawing............................................................................... 37
3.1.1

Processor Component Keep-Out Zones...................................................... 41

3.1.2

Package Loading Specifications ................................................................ 41

3.1.3

Package Handling Guidelines.................................................................... 41

3.1.4

Package Insertion Specifications............................................................... 42

3.1.5

Processor Mass Specification.................................................................... 42

3.1.6

Processor Materials................................................................................. 42

3.1.7

Processor Markings................................................................................. 42

3.1.8

Processor Land Coordinates ..................................................................... 45

Land Listing and Signal Descriptions ....................................................................... 47
4.1

Processor Land Assignments ............................................................................... 47

4.2

Alphabetical Signals Reference ............................................................................ 70

Thermal Specifications and Design Considerations .................................................. 79
5.1

Processor Thermal Specifications ......................................................................... 79
5.1.1

Thermal Specifications ............................................................................ 79

5.1.2

Thermal Metrology ................................................................................. 86

5.2

Processor Thermal Features ................................................................................ 86
5.2.1

Thermal Monitor..................................................................................... 86

5.2.2

Thermal Monitor 2 .................................................................................. 87

5.2.3

On-Demand Mode .................................................................................. 88

5.2.4

PROCHOT# Signal .................................................................................. 89