Intel E6540 HH80557PJ0534M User Manual

Product codes
HH80557PJ0534M
Page of 122
Electrical Specifications
30
Datasheet
.
2.7.3.1
GTL+ Front Side Bus Specifications
In most cases, termination resistors are not required as these are integrated into the 
processor silicon. See 
 for details on which GTL+ signals do not include on-die 
termination. 
Valid high and low levels are determined by the input buffers by comparing with a 
reference voltage called GTLREF
 lists the GTLREF specifications. The GTL+ 
reference voltage (GTLREF) should be generated on the system board using high 
precision voltage divider circuits. 
Table 14.
CMOS Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes
1
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
V
IL
Input Low Voltage 
-0.10
V
TT
 * 0.30
V
2, 3
2. V
IL
 is defined as the voltage range at a receiving agent that will be interpreted as a logical low 
value.
3. The V
TT
 referred to in these specifications refers to instantaneous V
TT
.
V
IH
Input High Voltage
V
TT
 * 0.70
V
TT 
+ 0.10
V
, 4, 5
4. V
IH
 is defined as the voltage range at a receiving agent that will be interpreted as a logical high 
value. 
5. V
IH
 and V
OH
 may experience excursions above V
TT
V
OL
Output Low Voltage
-0.10
V
TT
 * 0.10
V
V
OH
Output High Voltage
0.90 * V
TT
V
TT 
+ 0.10
V
, 6, 
6. All outputs are open drain.
I
OL
Output Low Current
1.70
4.70
mA
, 7
7. I
OL 
is measured at 0.10 * V
TT. 
I
OH 
is measured at 0.90 * V
TT.
I
OH
Output High Current
1.70
4.70
mA
I
LI
Input Leakage Current
N/A
± 100
µA
8
8. Leakage to V
SS
 with land held at V
TT
.
I
LO
Output Leakage Current
N/A
± 100
µA
9
9. Leakage to V
TT
 with land held at 300 mV.
Table 15.
GTL+ Bus Voltage Definitions
Symbol
Parameter
Min
Typ
Max
Units Notes
1
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
GTLREF_PU
GTLREF pull up resistor
124 * 0.99
124
124 * 1.01
Ω
2
2. GTLREF is to be generated from V
TT
 by a voltage divider of 1% resistors (one divider for each 
GTLEREF land). 
GTLREF_PD
GTLREF pull down resistor
210 * 0.99
210
210 * 1.01
Ω
R
TT
Termination Resistance
45
50
55
Ω
3
3. R
TT
 is the on-die termination resistance measured at V
TT
/3 of the GTL+ output driver. 
COMP[3:0]
COMP Resistance
49.40
49.90
50.40
Ω
4
4. COMP resistance must be provided on the system board with 1% resistors. See the applicable 
platform design guide for implementation details. COMP[3:0] and COMP8 resistors are tied to 
V
SS
.
COMP8
COMP Resistance
24.65
24.90
25.15
Ω