Intel AT80604004881AA User Manual

Intel® Xeon® Processor 7500 Datasheet, Volume 1

107

BOOTMODE[1:0]

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The BOOTMODE[1:0] inputs are to specify which mode the Intel® Xeon® processor 

7500 series will boot to. For details on the modes refer to the Intel® Xeon® 

Processor 7500 Series Datasheet, Volume 2. 

CVID[7:1]

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Voltage ID driven out to the VR 11.1 for dynamic/static adjustment of processor 

voltage set point. See VCACHE below. This signal has on die termination.

ERROR[0]_N

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Pulsed Signal. As output, signals un-corrected error condition of the processor. As an 

input, can be programmed to signal Intel® Scalable Memory Interconnect to the 

cores. Open drain

ERROR[1]_N

IO

Level Signal. As output, signals fatal error condition of the processor. As an input, 

can be programmed to signal Intel® Scalable Memory Interconnect to the cores. 

Open drain.

FBD0NBI[A/B][P/N][13:0]

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These differential pair data signals generated from the branch zero, channel A and B 

of Intel® Scalable Memory Interconnects are input to the Intel® Xeon® processor 

7500 series.

Example: FBD0NBIAP[0] Intel® Scalable Memory Interconnect branch 0, North 

bound data input lane 0 signal of channel A and positive bit of the differential pair. 

FBD0NBICLK[A/B][P/N]0 I

These 

differential pair clock signals generated from the branch zero, channel A and B 

of Intel® Scalable Memory Interconnects are input to the Intel® Xeon® processor 

7500 series.

Example: FBD0NBICLKAP0 Intel® Scalable Memory Interconnect branch 0, 

Northbound clock input signal of channel A and positive bit of the differential pair. 

FBD0SBO[A/B][P/N][10:0]

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These differential pair output data signals generated from Intel® Xeon® processor 

7500 series to the branch zero, channel A and B of Intel® Scalable Memory 

Interconnects.

Example: FBD0SBOAP[0] Intel® Scalable Memory Interconnect branch 1, 

southbound data output lane 0 signal of channel A and positive bit of the differential 

pair.

Interface 

Name

Branch 

Number

North 

Bound

Input

Channel

Differential 

Pair
Polarity 

Positive/

Negative

Lane 

Number

Interface 

Name

Branch 

Number

North 

Bound

Input

Clock

Channel

Differential 

Pair
Polarity 

Positive/

Negative

Interface 

Name

Branch 

Number

South 

Bound

Output

Channel

Differential 

Pair
Polarity 

Positive/

Negative

Lane 

Number