Intel AT80604004881AA User Manual

16

Intel® Xeon® Processor 7500 Datasheet, Volume 1

The VID[7:0], CVID[7:1], and VIO_VID[4:1] pins identify encoding that determine the 
voltage to be supplied by the VR to the socket Vcore, Vcache and VIO (the core, cache 
& system interface voltages for the Intel® Xeon® processor 7500 series) voltage 
regulators. The CoreVID and CacheVID specifications for the Intel® Xeon® processor 
7500 series are defined by VR 11.1. VIO_VID specifications for the Intel® Xeon® 
processor 7500 series are defined by VR 11.0. 

For CoreVID and CacheVID, individual processor VID values may be calibrated during 
manufacturing such that two devices at the same core speed may have different 
default VID settings. Furthermore, any of the Intel® Xeon® processor 7500 series can 
drive different VID settings during normal operation. For VIO_VID, all processors of a 
given stepping will have the same values.

The Voltage Identification (VID) specification for the Intel® Xeon® processor 7500 
series is defined by the Voltage Regulator Module (VRM) and Enterprise Voltage 
Regulator-Down (EVRD) 11.1 Design Guidelines. The voltage set by the VID signals is 
the reference VR output voltage to be delivered to the processor Vcc pins. VID signals 
are CMOS push/pull drivers. Please refer to 

 for the DC specifications for 

these signals. A voltage range is provided in 

 and changes with frequency. The 

specifications have been set such that one voltage regulator can operate with all 
supported frequencies. 

The Intel® Xeon® processor 7500 series

 

uses eight voltage identification signals, 

VID[7:0], to support automatic selection of power supply voltages. 

 specifies 

the voltage level corresponding to the state of VID[7:0]. A ‘1’ in this table refers to a 
high voltage level and a ‘0’ refers to a low voltage level. If the processor socket is 
empty (SKTOCC# high), or the voltage regulation circuit cannot supply the voltage that 
is requested, the voltage regulator must disable itself. See the Voltage Regulator 
Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.1 Design Guidelines 
for further details.

T

sustained 

storage

The minimum/maximum device 

storage temperature for a sustained 

period of time.

–5

40

°C

3,4

,

5

T

abs storage

The minimum/maximum device 

storage temperature beyond which 

damage (latent or otherwise) may 

occur when subjected to for any 

length of time.

-55

125

°C

3,4,5

RH

sustained 

storage

The maximum device storage relative 

humidity for a sustained period of 

time.

-

60%  @  24°C

3,4,5

Time

sustained 

storage

A prolonged or extended period of 

time; typically associated with 

sustained storage conditions.

0 months

12 months

3,4,5

1.

For functional operation, all processor electrical, signal quality, mechanical, and thermal specifications must 

be satisfied.

2.

Overshoot and undershoot voltage guidelines for input, output, and I/O signals are outlined in 

. 

Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.

3.

Storage conditions are applicable to storage environments only. In this scenario, the processor must not 

receive a clock, and no pins can be connected to a voltage bias. Storage within these limits will not affect 

the long-term reliability of the device. For functional operation, please refer to the processor case 

temperature specifications.

4.

This rating applies to the processor and does not include any packaging or trays.

5.

Failure to adhere to this specification can affect the long-term reliability of the processor.