Intel AT80604004881AA User Manual
4
Intel® Xeon® Processor 7500 Series Datasheet, Volume 1
PROCHOT_N Signal ............................................................................... 122
FORCE_PR_N Signal .............................................................................. 122
Platform Environment Control Interface (PECI) .................................................... 123
6.3.1
6.3.1
Features ................................................................................................................ 147
7.1
7.1
Introduction.................................................................................................... 147
Sideband Access to Processor Information ROM via SMBus .................................... 148
7.3.1
7.3.1
SMBus Memory Component Addressing............................................................... 151
Processor Uncore Data .......................................................................... 161
Figures
2-10 Input Device Hysteresis ......................................................................................45
2-11 RESET_N SEtup/Hold Time for Deterministic RESET_N Deassertion...........................48
2-12 THERMTRIP_N Power Down Sequence ..................................................................48
2-13 VID Step Times .................................................................................................49
2-14 SMBus Timing Waveform ....................................................................................50
2-15 SMBus Valid Delay Timing Waveform....................................................................50
2-16 FLASHROM Timing Waveform ..............................................................................51
2-17 TAP Valid Delay Timing Waveform........................................................................51
2-11 RESET_N SEtup/Hold Time for Deterministic RESET_N Deassertion...........................48
2-12 THERMTRIP_N Power Down Sequence ..................................................................48
2-13 VID Step Times .................................................................................................49
2-14 SMBus Timing Waveform ....................................................................................50
2-15 SMBus Valid Delay Timing Waveform....................................................................50
2-16 FLASHROM Timing Waveform ..............................................................................51
2-17 TAP Valid Delay Timing Waveform........................................................................51