Intel AT80604004881AA User Manual
Electrical Specifications
44
Intel® Xeon® Processor 7500 Datasheet, Volume 1
2.6
Platform Environmental Control Interface (PECI)
DC Specifications
PECI is an Intel proprietary interface that provides a communication channel between
Intel processors and chipset components to external thermal monitoring devices. The
Intel® Xeon® processor 7500 series contains a Digital Thermal Sensor (DTS) that
reports a relative die temperature as an offset from T
Intel processors and chipset components to external thermal monitoring devices. The
Intel® Xeon® processor 7500 series contains a Digital Thermal Sensor (DTS) that
reports a relative die temperature as an offset from T
CC
activation temperature.
Temperature sensors located throughout the die are implemented as analog-to-digital
converters calibrated at the factory. PECI provides an interface for external devices to
read processor die and DRAM temperatures, perform processor manageability
functions, and manage processor interface tuning and diagnostics.
converters calibrated at the factory. PECI provides an interface for external devices to
read processor die and DRAM temperatures, perform processor manageability
functions, and manage processor interface tuning and diagnostics.
2.6.1
DC Characteristics
The PECI interface operates at a nominal voltage set by V
IOC
. The set of DC electrical
is used with devices normally operating from a V
IOC
interface supply. V
IOC
nominal levels will vary between processor families. All PECI
devices will operate at the V
IOC
level determined by the processor installed in the
system. For specific nominal V
IOC
levels, refer to
Note:
1.
V
IOC
supplies the PECI interface. PECI behavior does not affect V
IOC
min/max specifications.
2.
It is expected that the PECI driver will take in to account, the variance in the receiver input thresholds and
consequently, be able to drive its output within safe limits (-0.15V to 0.275*V
IOC
for the low level and
0.725*V
IOC
to V
IOC
+0.15 for the high level).
3.
The leakage specification applies to powered devices on the PECI bus.
4.
One node is counted for each client and one node for the system host. Extended trace lengths might appear
as additional nodes.
5.
Excessive capacitive loading on the PECI line may slow down the signal rise/fall times and consequently
limit the maximum bit rate at which the interface can operate.
2.6.2
Input Device Hysteresis
The input buffers in both client and host models must use a Schmitt-triggered input
design for improved noise immunity. Use
design for improved noise immunity. Use
as a guide for input buffer design.
Table 2-23. PECI DC Electrical Limits
Symbol
Definition and Conditions
Min
Max
Units
Notes
1
V
in
Input Voltage Range
-0.150
V
IOC
+ 0.15
V
V
hysteresis
Hysteresis
0.1 * V
IOC
V
V
n
Negative-edge threshold voltage
0.275 * V
IOC
0.50 * V
IoC
V
2
V
p
Positive-edge threshold voltage
0.55 * V
IOC
0.725 * V
IOC
V
2
I
sink
Low level output sink
(V
OL
= 0.25 * V
IOC
)
0.5
1.0
mA
I
leak+
High impedance state leakage to
V
IOC
(V
leak
= V
OL
)
N/A
50
µA
3
I
leak-
High impedance leakage to GND
(V
leak
= V
OH
)
N/A
25
µA
3
C
bus
Bus capacitance per node
N/A
10
pF
4,5
V
noise
Signal noise immunity above
300 MHz
0.1 * V
IOC
N/A
V
p-p