Intel AT80604004881AA User Manual
Electrical Specifications
52
Intel® Xeon® Processor 7500 Datasheet, Volume 1
2.9
Processor AC Timing Waveforms
The following figures are used in conjunction with the AC timing tables,
through
Note:
, the following apply:
• All common clock AC timings signals are referenced to the Crossing Voltage
(V
CROSS
) of the SYSCLK_DP, SYSCLK_DN at rising edge of SYSCLK_DP.
• All source synchronous AC timings are referenced to their associated strobe
(address or data). Source synchronous data signals are referenced to the falling
edge of their associated data strobe. Source synchronous address signals are
referenced to the rising and falling edge of their associated address strobe.
edge of their associated data strobe. Source synchronous address signals are
referenced to the rising and falling edge of their associated address strobe.
• All AC timings for the TAP signals are referenced to the TCK at 0.5 * V
IO
at the
processor lands. All TAP signal timings (TMS, TDI, and so on) are referenced at 0.5
* V
* V
IO
at the processor die (pads).
• All CMOS signal timings are referenced at 0.5 * V
IO
at the processor lands.
.
Figure 2-18. Test Reset (TRST_N), Force_PR_N, RESET_N and PROCHOT_N Pulse Width
Waveform
V
T
q
T
q
= Pulse Width
V = 0.5*VCCIO
Figure 2-19. Intel® QPI System Interface Electrical Test Setup for Validating
Standalone TX Voltage and Timing Parameters
Tx Package
Silicon TX
Ideal Loads
SI Tx pin terminations are set to optimum values
(targeted around 42.5 ohms single-ended)
(targeted around 42.5 ohms single-ended)