Intel X3350 AT80569KJ067N Data Sheet
Product codes
AT80569KJ067N
Dual-Core Intel® Xeon® Processor 3000 Series Datasheet
11
Introduction
1
Introduction
The Dual-Core Intel
®
Xeon
®
processor 3000 series combines the performance of
previous generation products with the power efficiencies of a low-power
microarchitecture to enable smaller, quieter systems. These processors are 64-bit
processors that maintain compatibility with IA-32 software.
microarchitecture to enable smaller, quieter systems. These processors are 64-bit
processors that maintain compatibility with IA-32 software.
The Dual-Core Intel
®
Xeon
®
processor 3000 series uses Flip-Chip Land Grid Array
(FC-LGA6) package technology, and plugs into a 775-land surface mount, Land Grid
Array (LGA) socket, referred to as the LGA775 socket.
Array (LGA) socket, referred to as the LGA775 socket.
Note:
In this document unless otherwise specified, the Dual-Core Intel Xeon processor 3000
series refers to Dual-Core Intel Xeon processors 3085, 3075, 3070, 3065, 3060, 3050,
and 3040. Unless otherwise specified the Dual-Core Intel Xeon processor 3000 series is
referred to as “processor.”
The processors support several Advanced Technologies including the Execute Disable
Bit, Intel
Bit, Intel
®
64, and Enhanced Intel SpeedStep
®
Technology. In addition, the Dual-Core
Intel
®
Xeon
®
processor 3000 series supports Intel
®
Virtualization Technology
(Intel
®
VT) and Intel
®
Trusted Execution Technology (Intel
®
TXT).
The processor's front side bus (FSB) uses a split-transaction, deferred reply protocol
like the Intel
like the Intel
®
Pentium
®
4 processor. The FSB uses Source-Synchronous Transfer (SST)
of address and data to improve performance by transferring data four times per bus
clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address
bus can deliver addresses two times per bus clock and is referred to as a "double-
clocked" or 2X address bus. Working together, the 4X data bus and 2X address bus
provide a data bus bandwidth of up to
clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address
bus can deliver addresses two times per bus clock and is referred to as a "double-
clocked" or 2X address bus. Working together, the 4X data bus and 2X address bus
provide a data bus bandwidth of up to
8.5
10.7 GB/s.
Intel has enabled support components for the processor including heatsink, heatsink
retention mechanism, and socket. Manufacturability is a high priority; hence,
mechanical assembly may be completed from the top of the baseboard and should not
require any special tooling.
retention mechanism, and socket. Manufacturability is a high priority; hence,
mechanical assembly may be completed from the top of the baseboard and should not
require any special tooling.
The processor includes an address bus power-down capability which removes power
from the address and data signals when the FSB is not in use. This feature is always
enabled on the processor.
from the address and data signals when the FSB is not in use. This feature is always
enabled on the processor.
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in
the active state when driven to a low level. For example, when RESET# is low, a reset
has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary series (such as address or data), the ‘#’ symbol implies that
the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# =
‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
the active state when driven to a low level. For example, when RESET# is low, a reset
has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary series (such as address or data), the ‘#’ symbol implies that
the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# =
‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
The phrase “Front Side Bus” refers to the interface between the processor and system
core logic (a.k.a. the chipset components). The FSB is a multiprocessing interface to
processors, memory, and I/O.
core logic (a.k.a. the chipset components). The FSB is a multiprocessing interface to
processors, memory, and I/O.