Intel LF80550KG0804M Data Sheet
Introduction
12
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
The Dual-Core Intel Xeon processor 7100 series processor supports Intel® 64 as an
enhancement to Intel’s IA-32 architecture. This enhancement allows the processor to
execute operating systems and applications written to take advantage of the 64-bit
extension technology. Further details can be found in the 64-bit Extension Technology
Software Developer’s Guide at http://developer.intel.com/technology/64bitextensions/.
enhancement to Intel’s IA-32 architecture. This enhancement allows the processor to
execute operating systems and applications written to take advantage of the 64-bit
extension technology. Further details can be found in the 64-bit Extension Technology
Software Developer’s Guide at http://developer.intel.com/technology/64bitextensions/.
Dual-Core Intel Xeon processor 7100 series are intended for high performance multi-
processor server systems with support for up to two processors on a 667 or 800 MTS
FSB. Dual-Core Intel Xeon processor 7100 series will be available with 4 MB, 8 MB or
16 MB of on-die level 3 (L3) cache. All versions of the Dual-Core Intel Xeon processor
7100 series will include manageability features. Components of the manageability
features include an OEM EEPROM and Processor Information ROM which are accessed
through an SMBus interface and contain information relevant to the particular
processor and system in which it is installed.
processor server systems with support for up to two processors on a 667 or 800 MTS
FSB. Dual-Core Intel Xeon processor 7100 series will be available with 4 MB, 8 MB or
16 MB of on-die level 3 (L3) cache. All versions of the Dual-Core Intel Xeon processor
7100 series will include manageability features. Components of the manageability
features include an OEM EEPROM and Processor Information ROM which are accessed
through an SMBus interface and contain information relevant to the particular
processor and system in which it is installed.
Notes:
1.
Total accessible size of L2 caches may vary by one cache line pair (128 bytes) per core, depending on
usage and operating environment.
2.
Total accessible size of the L3 cache may vary by up to thirty-two (32) cache lines (64 bytes per line),
depending on usage and operating environment.
The Dual-Core Intel Xeon processor 7100 series is packaged in a 604-pin Flip-Chip
Micro Pin Grid Array (FC-mPGA6) package and utilizes a surface-mount Zero Insertion
Force (ZIF) mPGA604 socket. The Dual-Core Intel Xeon processor 7100 series supports
40-bit addressing, data bus ECC protection (single-bit error correction with double-bit
error detection), and the bus protocol addition of the Deferred Phase.
Micro Pin Grid Array (FC-mPGA6) package and utilizes a surface-mount Zero Insertion
Force (ZIF) mPGA604 socket. The Dual-Core Intel Xeon processor 7100 series supports
40-bit addressing, data bus ECC protection (single-bit error correction with double-bit
error detection), and the bus protocol addition of the Deferred Phase.
The Dual-Core Intel Xeon processor 7100 series uses a scalable system bus protocol
referred to as the “front side bus” in this document. The front side bus utilizes a split-
transaction, deferred reply and Deferred Phase protocol. The front side bus uses
Source-Synchronous Transfer (SST) of address and data to improve performance. The
processor transfers data four times per bus clock (4X data transfer rate). Along with
the 4X data bus, the address bus can deliver addresses two times per bus clock and is
referred to as a ‘double-clocked’, ‘double-pumped’, or the 2X address bus. In addition,
the Request Phase completes in one clock cycle. Working together, the 4X data bus and
2X address bus provide a data bus bandwidth of up to 5.3 GB (667 MTS) or 6.4 GB
(800 MTS) per second. Finally, the front side bus is also used to deliver interrupts.
referred to as the “front side bus” in this document. The front side bus utilizes a split-
transaction, deferred reply and Deferred Phase protocol. The front side bus uses
Source-Synchronous Transfer (SST) of address and data to improve performance. The
processor transfers data four times per bus clock (4X data transfer rate). Along with
the 4X data bus, the address bus can deliver addresses two times per bus clock and is
referred to as a ‘double-clocked’, ‘double-pumped’, or the 2X address bus. In addition,
the Request Phase completes in one clock cycle. Working together, the 4X data bus and
2X address bus provide a data bus bandwidth of up to 5.3 GB (667 MTS) or 6.4 GB
(800 MTS) per second. Finally, the front side bus is also used to deliver interrupts.
The Dual-Core Intel Xeon processor 7100 series supports a threshold-based
mechanism for enhanced cache error reporting (IA32_MCG_CAP[11] = 1). Intel
recommends that fault prediction handlers rely on this mechanism to assess processor
cache health. Please refer to the IA-32 Intel® Architecture Software Developer’s
Manual, Volume 3A for more detailed information. Please note that the Dual-Core Intel
Xeon processor 7100 series does not support the newly added overwrite rules.
mechanism for enhanced cache error reporting (IA32_MCG_CAP[11] = 1). Intel
recommends that fault prediction handlers rely on this mechanism to assess processor
cache health. Please refer to the IA-32 Intel® Architecture Software Developer’s
Manual, Volume 3A for more detailed information. Please note that the Dual-Core Intel
Xeon processor 7100 series does not support the newly added overwrite rules.
Table 1-1.
Features of the Dual-Core Intel® Xeon® Processor 7100 Series
# of Supported
Symmetric Agents
Per FSB
L2 Advanced
Transfer Cache
1
Integrated L3
Cache
2
FSB
Frequency
Dual-Core Intel®
Xeon® Processor
7100 Series
1 - 2
2 MB total
(1 MB per core)
4 MB, 8 MB or
16 MB
667 or
800 MTS