Cisco Cisco Packet Data Gateway (PDG) Maintenance Manual
New Feature Summary
Generally Available 06-30-2010
1-4
redundant pairs prior to configuring the interface bindings so that proper parallel physical
and logical port configurations are established. The card redundancy and monitoring begins
as soon as the PSC or PSC2 in front is active.
and logical port configurations are established. The card redundancy and monitoring begins
as soon as the PSC or PSC2 in front is active.
Note: Side-by-side 1:1 redundancy only operates on top line card slot numbers: cards 17
through 23 and 26 through 32. Make sure that both PSCs or PSC2s in front of the line cards
are of the same type, configured as a redundant pair, and active.
through 23 and 26 through 32. Make sure that both PSCs or PSC2s in front of the line cards
are of the same type, configured as a redundant pair, and active.
For more information on side by side 1:1 redundancy for 10 Gig line card (XGLC), refer
ST40 Hardware Installation Guide.
ST40 Hardware Installation Guide.
Packet Processor Card (PPC)
The PPC has features a quad-core x86 2.5Ghz CPU and 16GB of RAM. The processor runs
a single copy of the operating system. To check the CPU in the CLI, use the
a single copy of the operating system. To check the CPU in the CLI, use the
show cpu
table
command. The operating system running on the PPC treats the dual-core processor as
a 2-way multi-processor. You can see this in the output of the
show cpu info verbose
command.
I
MPORTANT
For this release, the PPC is limited to CDMA and HA functionality.
A second-generation data transport fixed programmable gate array (DT2 FPGA,
abbreviated as DT2) connects the PPC’s NPU bus to the switch fabric interface. The FPGA
also provides a bypass path between the line card or Redundancy Crossbar Card (RCC) and
the switch fabric for ATM traffic. Traffic from the line cards or the RCC is received over the
FPGA’s serial links and is sent to the NPU on its switch fabric interface. The traffic destined
for the line cards or RCC is diverted from the NPU interface and sent over the serial links.
abbreviated as DT2) connects the PPC’s NPU bus to the switch fabric interface. The FPGA
also provides a bypass path between the line card or Redundancy Crossbar Card (RCC) and
the switch fabric for ATM traffic. Traffic from the line cards or the RCC is received over the
FPGA’s serial links and is sent to the NPU on its switch fabric interface. The traffic destined
for the line cards or RCC is diverted from the NPU interface and sent over the serial links.
DT2 FPGA also connects to the control processors subsystem via a PCI-E bus. The PCI-E
interface allows the control processors to perform register accesses to the FPGA and some
components attached to it, and also allows DMA operations between the NPU and the
control processors’ memory. A statistics engine is provided in the FPGA. Two reduced
latency DRAM (RLDRAM) chips attached to the FPGA provide 64MB of storage for
counters.
interface allows the control processors to perform register accesses to the FPGA and some
components attached to it, and also allows DMA operations between the NPU and the
control processors’ memory. A statistics engine is provided in the FPGA. Two reduced
latency DRAM (RLDRAM) chips attached to the FPGA provide 64MB of storage for
counters.
The PPC has a 2.5 G/bps-based security processor that provides the highest performance for
cryptographic acceleration of next-generation IP Security (IPsec), Secure Sockets Layer
(SSL) and wireless LAN/WAN security applications with the latest security algorithms.
cryptographic acceleration of next-generation IP Security (IPsec), Secure Sockets Layer
(SSL) and wireless LAN/WAN security applications with the latest security algorithms.
Redundancy
●
The PPC is fully redundant with a spare PPC.
Capacity
●
3 million SAU and 6 million PDP contexts
●
2 million PDSN sessions
●
6 million HA sessions