Kingston Technology KHX1333C7AD3/2G Data Sheet
Memory Module Specifications
KHX1333C7AD3/2G
2GB 256M x 64-Bit DDR3-1333MHz
CL7 240-Pin DIMM
CL7 240-Pin DIMM
Kingston.com
Document No. 4805838-001.B00 07/18/11 Page 1
DESCRIPTION
This document describes Kingston’s 256M x 64-bit (2GB)
DDR3-1333MHz CL7 SDRAM (Synchronous DRAM) memory
module, based on sixteen 128M x 8-bit DDR3 FBGA compo-
nents. This module has been tested to run at DDR3-1333MHz
at a low latency timing of 7-7-7-20 at 1.65V. The SPD is
programmed to JEDEC standard latency DDR3-1333MHz
timing of 9-9-9 at 1.5V. This 240-pin DIMM uses gold contact
fingers and requires +1.5V. The JEDEC standard electrical
and mechanical specifications are as follows:
DDR3-1333MHz CL7 SDRAM (Synchronous DRAM) memory
module, based on sixteen 128M x 8-bit DDR3 FBGA compo-
nents. This module has been tested to run at DDR3-1333MHz
at a low latency timing of 7-7-7-20 at 1.65V. The SPD is
programmed to JEDEC standard latency DDR3-1333MHz
timing of 9-9-9 at 1.5V. This 240-pin DIMM uses gold contact
fingers and requires +1.5V. The JEDEC standard electrical
and mechanical specifications are as follows:
SPECIFICATIONS
CL(IDD)
9 cycles
Row Cycle Time (tRCmin)
49.5ns (min.)
Refresh to Active/Refresh
110ns
Command Time (tRFCmin)
Row Active Time (tRASmin)
36ns (min.)
Power
1.800 W (operating)
UL Rating
94 V - 0
Operating Temperature
0° C to 85° C
Storage Temperature
-55° C to +100° C
FEATURES
• JEDEC standard 1.5V ± 0.075V Power Supply
• VDDQ = 1.5V ± 0.075V
• 667MHz fCK for 1333Mb/sec/pin
• 8 independent internal bank
• Programmable CAS Latency: 5,6,7,8,9,10
• Posted CAS
• Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency(CWL) = 7(DDR3-1333)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with
• VDDQ = 1.5V ± 0.075V
• 667MHz fCK for 1333Mb/sec/pin
• 8 independent internal bank
• Programmable CAS Latency: 5,6,7,8,9,10
• Posted CAS
• Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency(CWL) = 7(DDR3-1333)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with
starting address “000” only), 4 with tCCD = 4 which does not al-
low seamless read or write [either on the fly using A12 or MRS]
low seamless read or write [either on the fly using A12 or MRS]
• Bi-directional Differential Data Strobe
• Internal(self) calibration : Internal self calibration through ZQ
• Internal(self) calibration : Internal self calibration through ZQ
pin (RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE 85°C,
• Average Refresh Period 7.8us at lower than TCASE 85°C,
3.9us at 85°C < TCASE ≤ 95°C
• Asynchronous Reset
• PCB : Height 1.180” (30.00mm), double sided component
• PCB : Height 1.180” (30.00mm), double sided component
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