Gateway Intel Xeon L5520 TC.32500.005 User Manual

84

Intel® Xeon® Processor 5500 Series Datasheet, Volume 2

Provides the status of the operation specified in MC_SSRCONTROL.SSR_Mode.

Per Dimm counters of correctable ECC errors. The register organization is as follows. 
For example, if there are three DIMMS on the channel, MC_COR_ECC_CNT_0 contains 
the error counter information for DIMM 0 and DIMM1 on Channel 0. 
MC_COR_ECC_CNT_1 contains the error counter information for DIMM2 on Channel 0.

The lower 16-bit of MC_COR_ECC_CNT_0 contains the errors for DIMM0 and the upper 
16-bit field contains the errors for DIMM1. The lower 16-bit of MC_COR_ECC_CNT_1 
contains the errors for DIMM2. The upper 16 bits of MC_COR_ECC_CNT_1 are not 
used. The same organization applies to Channel 1 and Channel 2.

MC_COR_ECC_CNT_0 : Channel 0 Dimm 0/1
MC_COR_ECC_CNT_1 : Channel 0 Dimm 2/Rsvd
MC_COR_ECC_CNT_2 : Channel 1 Dimm 0/1
MC_COR_ECC_CNT_3 : Channel 1 Dimm 2/Rsvd
MC_COR_ECC_CNT_4 : Channel 2 Dimm 0/1
MC_COR_ECC_CNT_5 : Channel 2 Dimm 2/Rsvd

If there are one or two DIMMS on the channel, the lower 16-bit field of 
MC_COR_ECC_CNT_0 contains the errors for DIMM0 on Ranks 0 and 1 on Channel 0.   
The upper 16-bit field contains information for DIMM0 on Ranks 2 and 3 for a quad rank 
DIMM. The same organization follows for DIMM1 for MC_COR_ECC_CNT_1.

MC_COR_ECC_CNT_0 : Channel 0 Dimm 0 Ranks 0,1/2,3
MC_COR_ECC_CNT_1 : Channel 0 Dimm 1 Ranks 0,1/2,3
MC_COR_ECC_CNT_2 : Channel 1 Dimm 0 Ranks 0,1/2,3
MC_COR_ECC_CNT_3 : Channel 1 Dimm 1 Ranks 0,1/2,3
MC_COR_ECC_CNT_4 : Channel 2 Dimm 0 Ranks 0,1/2,3
MC_COR_ECC_CNT_5 : Channel 2 Dimm 1 Ranks 0,1/2,3

1

RO

0

INPROGRESS. Patrol Scrub operation in progress. This bit is set by hardware 

once scrubbing operation has started. It is cleared once operation is complete 

or fails.

0

RO

0

CMPLT. Patrol Scrub operation complete. Set by hardware once operation is 

complete. Bit is cleared by hardware when a new operation is enabled.