Intel X5667 AT80614005154AB User Manual
Product codes
AT80614005154AB
Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1
53
Electrical Specifications
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
All AC timings for the Asynchronous GTL signals are referenced to the BCLK_P rising edge at Crossing
Voltage (V
CROSS
). VCCPWRGOOD, VTTPWRGOOD and VDDPWRGOOD are referenced to BCLK_P rising edge
at 0.5 * V
TT
.
3.
These signals may be driven asynchronously.
4.
Refer to
for additional timing requirements for entering and leaving low power states.
5.
xxPWRGOOD signal has no edge rate requirement, but edge must be monotonic.
6.
VDDPWRGOOD must be asserted no later then VCCPWRGOOD. There is no releationship between
VDDPWRGOOD and VCC ramp.
7.
There is no dependency between VDDPWRGOOD and VTTPWRGOOD assertion.
8.
VTTPWRGOOD must accurately reflect the state of VTT and must not glitch whenever VTT or VDD is
applied.
9.
VTT must read VTTFINAL before VCCPWRGOOD assertion.
10. It may be required to add delay on the board to meet the 1 ms minimum processor requirement.
11. Based on a test load of 50 Ω to V
TT
.
12. Specified for synchronous signals.
13. Applies to PROCHOT# signal only. Please see
for information regarding
Power-On Configuration options.
14. Rise time is measured from 10% to 90% of the final voltage.
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Not 100% tested. Specified by design characterization.
3.
It is recommended that TMS be asserted while TRST# is being deasserted.
Notes:
1.
Platform support for VID transitions is required for the processor to operate within specifications.
VTTPWRGOOD de-assertion to V
TT
below specification
100
ns
T
CO
: Time from BCLK land until signal valid at output
0.5
2.275
ns
11
T
SU
: Processor Sideband Input signals with respect to
BCLK
600
ps
12
T
H
: Processor Sideband Input signals with respect to
BCLK
600
ps
T
H
: Power-On Configuration Hold Time (PROCHOT#)
106
BCLK
13
Table 2-26. Processor Sideband Signal Group AC Specifications (Sheet 2 of 2)
T# Parameter
Min
Max
Unit
Figure
Notes
1,2,3,4
Table 2-27. TAP Signal Group AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes
1,2,3
TCK Period
31.25
ns
T
s
: TDI, TMS Setup Time
1
ns
T
h
: TDI, TMS Hold Time
1
ns
T
x
: TDO Clock to Output Delay
0.5
4
ns
T
q
: TRST# Assert Time
2
T
TCK
Table 2-28. VID Signal Group AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes
1
Ta: VID Step Time
1.25
µs
Tb: VID Down Transition to Valid V
CC
(min)
0
µs
Tc: VID Up Transition to Valid V
CC
(min)
15
µs
Td: VID Down Transition to Valid V
CC
(max)
15
µs
Te: VID Up Transition to Valid V
CC
(max)
0
µs