Intel i7-640M CN80617006936AA User Manual

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Datasheet

The eDP interface is physically shared with a subset of the PCIe interface. Specifically, 

eDP[3:0] map to Logical Lanes PEG[12:15] of the PCIe interface. Mapping for reversed 

case is: eDP[3:0] maps to PEG[3:0], ex: eDP[0]=PEG[15] in non reversed case. In 

reversed case: eDP[0] = PEG[0].

When eDP is enabled, the lower logical lanes are still available for standard PCIe 

devices, using the PEG 0 controller. PEG 0 is limited to x1. The board manufacture 

chooses whether to use eDP and whether to use lane numbering reversal.

The eDP interface supports link-speeds of 1.62 Gbps and 2.7 Gbps on 1, 2 or 4 data 

lanes. The eDP and PCI Express x1 may be supported concurrently. eDP interface may 

support -0.5% SSC and non-SSC clock settings.

The Intel Flexible Display Interface (Intel FDI) is a proprietary link for carrying display 

traffic from the integrated graphics controller to the PCH display I/O’s. Intel FDI 

supports two independent channels; one for pipe A and one for pipe B.

• Each channel has four transmit (Tx) differential pairs used for transporting pixel 

and framing data from the display engine. 

• Each channel has one single-ended LineSync and one FrameSync input (1-V CMOS 

signaling).

• One display interrupt line input (1-V CMOS signaling).
• Intel FDI may dynamically scalable down to 2X or 1X based on actual display 

bandwidth requirements. 

• Common 100-MHz reference clock is sent to both processor and PCH.
• Each channel transports at a rate of 2.7 Gbps.
• PCH supports end-to-end lane reversal across both channels (no reversal support 

required)

eDP_AUX

PEG_RX[13]

PEG_RX[2]

eDP_AUX#

PEG_RX#[13]

PEG_RX#[2]

eDP_HPD#

PEG_RX[12]

PEG_RX[3]

eDP_TX[0]

PEG_TX[15]

PEG_TX[0]

eDP_TX#[0]

PEG_TX#[15]

PEG_TX#[0]

eDP_TX[1]

PEG_TX[14]

PEG_TX[1]

eDP_TX#[1]

PEG_TX#[14]

PEG_TX#[1]

eDP_TX[2]

PEG_TX[13]

PEG_TX[2]

eDP_TX#[2]

PEG_TX#[13]

PEG_TX#[2]

eDP_TX[3]

PEG_TX[12]

PEG_TX[3]

eDP_TX#[3]

PEG_TX#[12]

PEG_TX#[3]