Intel i7-640M CN80617006936AA User Manual

Datasheet

43

The following are the key features of Enhanced Intel SpeedStep Technology:

• Multiple frequency and voltage points for optimal performance and power 

efficiency. These operating points are known as P-states.

• Frequency selection is software controlled by writing to processor MSRs. The 

voltage is optimized based on the selected frequency and the number of active 

processor cores.

— If the target frequency is higher than the current frequency, V

CC

 is ramped up 

in steps to an optimized voltage. This voltage is signaled by the VID[6:0] pins 

to the voltage regulator. Once the voltage is established, the PLL locks on to the 

target frequency.

— If the target frequency is lower than the current frequency, the PLL locks to the 

target frequency, then transitions to a lower voltage by signaling the target 

voltage on the VID[6:0] pins.

— All active processor cores share the same frequency and voltage. In a multi-

core processor, the highest frequency P-state requested amongst all active 

cores is selected.

— Software-requested transitions are accepted at any time. If a previous 

transition is in progress, the new transition is deferred until the previous 

transition is completed.

• The processor controls voltage ramp rates internally to ensure glitch-free 

transitions.

• Because there is low transition latency between P-states, a significant number of 

transitions per-second are possible.

When the processor is idle, low-power idle states (C-states) are used to save power. 

More power savings actions are taken for numerically higher C-states. However, higher 

C-states have longer exit and entry latencies. Resolution of C-states occur at the 

thread, processor core, and processor package level. Thread-level C-states are 

available if Intel Hyper-Threading Technology is enabled.

Processor Package State

Core 1 State

Thread 1

Thread 0

Core 0 State

Thread 1

Thread 0