Intel i7-640M CN80617006936AA User Manual

Intel

Product codes

CN80617006936AA

6

Datasheet

Power and Ground Pins.......................................................................................83

Decoupling Guidelines ........................................................................................83
7.2.1

Voltage Rail Decoupling ...........................................................................83

Processor Clocking (BCLK, BCLK#).......................................................................83
7.3.1

PLL Power Supply ...................................................................................83

Voltage Identification (VID).................................................................................84

Reserved or Unused Signals ................................................................................88

Signal Groups ...................................................................................................89

Test Access Port (TAP) Connection .......................................................................91

Absolute Maximum and Minimum Ratings..............................................................92

Storage Conditions Specifications.........................................................................92

7.10 DC Specifications ...............................................................................................93

7.10.1 Voltage and Current Specifications ............................................................94

7.11 Platform Environmental Control Interface (PECI) DC Specifications ......................... 103

7.11.1 DC Characteristics ................................................................................ 103
7.11.2 Input Device Hysteresis ......................................................................... 104

Processor Pin and Signal Information .................................................................... 105
8.1

Processor Pin Assignments ................................................................................ 105

Package Mechanical Information ........................................................................ 178

Figures

Intel® Core™ i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series Processor on

the Calpella Platform.................................................................................................11

Intel Flex Memory Technology Operation .....................................................................22

Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes ...................23

PCI Express Layering Diagram....................................................................................25

Packet Flow through the Layers ..................................................................................25

PCI Express Related Register Structures ......................................................................26

Integrated Graphics Controller Unit Block Diagram........................................................28

Processor Display Block Diagram ................................................................................30

Idle Power Management Breakdown of the Processor Cores............................................43

10 Thread and Core C-State Entry and Exit ......................................................................44
11 Package C-State Entry and Exit ..................................................................................47
12 Frequency and Voltage Ordering.................................................................................59
13 Active V

CC

and I

CC

Loadline (PSI# Asserted) ................................................................95

CC

and I

CC

Loadline (PSI# Not Asserted) ..........................................................96

15 VAXG/IAXG Static and Ripple Voltage Regulation .........................................................99
16 Input Device Hysteresis........................................................................................... 104
17 Socket-G (rPGA988A) Pinmap (Top View, Upper-Left Quadrant).................................... 106
18 Socket-G (rPGA988A) Pinmap (Top View, Upper-Right Quadrant).................................. 107
19 Socket-G (rPGA988A) Pinmap (Top View, Lower-Left Quadrant).................................... 108
20 Socket-G (rPGA988A) Pinmap (Top View, Lower-Right Quadrant).................................. 109
21 BGA1288 Ballmap (Top View, Upper-Left Quadrant) .................................................... 138
22 BGA1288 Ballmap (Top View, Upper-Right Quadrant) .................................................. 139
23 BGA1288 Ballmap (Top View, Lower-Left Quadrant) .................................................... 140
24 BGA1288 Ballmap (Top View, Lower-Right Quadrant) .................................................. 141
25 rPGA Mechanical Package (Sheet 1 of 2).................................................................... 178
26 rPGA Mechanical Package (Sheet 2 of 2).................................................................... 179
27 BGA Mechanical Package (Sheet 1 of 2)..................................................................... 180
28 BGA Mechanical Package (Sheet 2 of 2)..................................................................... 181