Intel i7-640M CN80617006936AA User Manual

70

Datasheet

SA_CK#[1:0]

SDRAM Inverted Differential Clock: 
Channel A SDRAM Differential clock signal-
pair complement.

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DDR3

SA_CKE[1:0]

Clock Enable: (1 per rank) Used to:
- Initialize the SDRAMs during power-up
- Power-down SDRAM ranks
- Place all SDRAM ranks into and out of self-
refresh during STR

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DDR3

SA_CS#[1:0]

Chip Select: (1 per rank) Used to select 
particular SDRAM components during the 
active state. There is one Chip Select for 
each SDRAM rank.

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DDR3

SA_ODT[1:0]

On Die Termination: Active Termination 
Control.

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DDR3

SB_BS[2:0]

Bank Select: These signals define which 
banks are selected within each SDRAM rank.

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DDR3

SB_WE#

Write Enable Control Signal: Used with 
SB_RAS# and SB_CAS# (along with 
SB_CS#) to define the SDRAM Commands.

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DDR3

SB_RAS#

RAS Control Signal: Used with SB_CAS# 
and SB_WE# (along with SB_CS#) to define 
the SRAM Commands.

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DDR3

SB_CAS#

CAS Control Signal: Used with SB_RAS# 
and SB_WE# (along with SB_CS#) to define 
the SRAM Commands.

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DDR3

SB_DM[7:0]

Data Mask: These signals are used to mask 
individual bytes of data in the case of a 
partial write and to interrupt burst writes.  
When activated during writes, the 
corresponding data groups in the SDRAM are 
masked.  There is one SB_DM[7:0] for every 
data byte lane.

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DDR3

SB_DM[7:0]

Data Mask: These signals are used to mask 
individual bytes of data in the case of a 
partial write, and to interrupt burst writes. 
When activated during writes, the 
corresponding data groups in the SDRAM are 
masked. There is one SB_DM[7:0] for every 
data byte lane.

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DDR3