Intel 2 Duo T6500 AW80577GG0452MA User Manual

Datasheet

17

state, it will not respond to interrupts or snoop transactions. Any transition on an input 

signal before the processor has returned to Stop-Grant state will result in unpredictable 

behavior.

The Deeper Sleep state is similar to the Deep Sleep state but further reduces core 

voltage levels. One of the potential lower core voltage levels is achieved by entering the 

base Deeper Sleep state. The Deeper Sleep state is entered through assertion of the 

DPRSTP# pin while in the Deep Sleep state. The following lower core voltage level is 

achieved by entering the Intel Enhanced Deeper Sleep state which is a sub-state of 

Deeper Sleep state. Intel Enhanced Deeper Sleep state is entered through assertion of 

the DPRSTP# pin while in the Deep Sleep only when the L2 cache has been completely 

shut down. Refer to 

 and 

 for further details on 

reducing the L2 cache and entering Intel Enhanced Deeper Sleep state.

In response to entering Deeper Sleep, the processor drives the VID code corresponding 

to the Deeper Sleep core voltage on the VID[6:0] pins. 

Exit from Deeper Sleep or Intel Enhanced Deeper Sleep state is initiated by DPRSTP# 

deassertion when either core requests a core state other than C4 or either core 

requests a processor performance state other than the lowest operating point. 

Intel Enhanced Deeper Sleep state is a sub-state of Deeper Sleep that extends power-

saving capabilities by allowing the processor to further reduce core voltage once the L2 

cache has been reduced to zero ways and completely shut down. The following events 

occur when the processor enters Intel Enhanced Deeper Sleep state:

• The last core entering C4 issues a P_LVL4 or P_LVL5 I/O read or an MWAIT(C4) 

instruction and then progressively reduces the L2 cache to zero

• Once the L2 cache has been reduced to zero, the processor triggers a special 

chipset sequence to notify the chipset to redirect all FSB traffic, except APIC 

messages, to memory. The snoops are replied as misses by the chipset and are 

directed to main memory instead of the L2 cache. This allows for higher residency 

of the processor’s Intel Enhanced Deeper Sleep state.

• The processor drives the VID code corresponding to the Intel Enhanced Deeper 

Sleep state core voltage on the VID[6:0] pins.

When both cores have entered the CC6 state and the L2 cache has been shrunk down 

to zero ways, the processor will enter the Deep Power Down Technology state. To do so 

both cores save their architectural states in the on-die SRAM that resides in the V

CCP

 

domain. At this point, the core V

CC

 will be dropped to the lowest core voltage closer to 

0-V. The processor is now in an extremely low-power state. 

In Intel Deep Power Down Technology state, the processor does not need to be 

snooped as all the caches are flushed before entering this state.