Intel 2 Duo T6500 AW80577GG0452MA User Manual

Datasheet

95

DEFER#

Input

DEFER# is asserted by an agent to indicate that a transaction 
cannot be ensured in-order completion. Assertion of DEFER# is 
normally the responsibility of the addressed memory or input/
output agent. This signal must connect the appropriate pins of both 
FSB agents.

DINV[3:0]#

Input/

Output

DINV[3:0]# (Data Bus Inversion) are source synchronous and 
indicate the polarity of the D[63:0]# signals. The DINV[3:0]# 
signals are activated when the data on the data bus is inverted. The 
bus agent will invert the data bus signals if more than half the bits, 
within the covered group, would change level in the next cycle.

DPRSTP#

Input

DPRSTP#, when asserted on the platform, causes the processor to 
transition from the Deep Sleep State to the Deeper Sleep state or 
Deep Power Down Technology (C6) state. To return to the Deep 
Sleep State, DPRSTP# must be deasserted. DPRSTP# is driven by 
the ICH9M.

DPSLP#

Input

DPSLP# when asserted on the platform causes the processor to 
transition from the Sleep State to the Deep Sleep state. To return to 
the Sleep State, DPSLP# must be deasserted. DPSLP# is driven by 
the ICH9M.

DPWR#

Input/

Output

DPWR# is a control signal used by the chipset to reduce power on 
the processor data bus input buffers. The processor drives this pin 
during dynamic FSB frequency switching

.

DRDY#

Input/

Output

DRDY# (Data Ready) is asserted by the data driver on each data 
transfer, indicating valid data on the data bus. In a multi-common 
clock data transfer, DRDY# may be deasserted to insert idle clocks. 
This signal must connect the appropriate pins of both FSB agents.

DSTBN[3:0]#

Input/

Output

Data strobe used to latch in D[63:0]#.

DINV[3]#

D[63:48]#

DINV[2]#

D[47:32]#

DINV[1]#

D[31:16]#

DINV[0]#

D[15:0]#

D[15:0]#, DINV[0]# 

DSTBN[0]#

D[31:16]#, DINV[1]# 

DSTBN[1]#

D[47:32]#, DINV[2]# 

DSTBN[2]#

D[63:48]#, DINV[3]# 

DSTBN[3]#