AMD athlon 64 User Manual
Chapter 2
Experimental Setup
13
Performance Guidelines for AMD Athlon™ 64 and AMD Opteron™
ccNUMA Multiprocessor Systems
40555
Rev. 3.00
June 2006
Chapter 2
Experimental Setup
This chapter presents a description of the experimental environment within which the following
performance study was carried out. This section describes the hardware configuration and the
software test framework used.
performance study was carried out. This section describes the hardware configuration and the
software test framework used.
2.1
System Used
All experiments and analysis discussed in this application note were performed on a Quartet system
having four 2.2 GHz E1 Dual-Core AMD Opteron™ processors running the Linux
having four 2.2 GHz E1 Dual-Core AMD Opteron™ processors running the Linux
®
2.6.12-rc1-mm1
kernel (ccNUMA-aware kernel).
While Quartet is an internal development non-commercial platform, the way the processors are
connected on the Quartet is a common way of connecting and routing the processors on other
supported 4P AMD platforms. We anticipate that these results should hold on other systems that are
connected in a similar manner and we expect the recommendations to carry forward on the current
generation Opteron systems. We also expect that the results will hold on other Linux kernels and even
other operating systems for reasons explained later.
connected on the Quartet is a common way of connecting and routing the processors on other
supported 4P AMD platforms. We anticipate that these results should hold on other systems that are
connected in a similar manner and we expect the recommendations to carry forward on the current
generation Opteron systems. We also expect that the results will hold on other Linux kernels and even
other operating systems for reasons explained later.
Each processor had 2x1GB DDR400 CL2.5 PC3200 (Samsung K4H510838B-TCCC) DRAM
memory. To rule out any interference from the Xserver and the network, all tests were performed at
runlevel 3 with the network disconnected.
memory. To rule out any interference from the Xserver and the network, all tests were performed at
runlevel 3 with the network disconnected.
At a high level, in a Quartet, the four dual-core processors are connected with coherent
HyperTransport™ links. Each processor has one bidirectional HyperTransport link that is dedicated
to I/O and two bidirectional coherent HyperTransport links that are used to connect to two other dual-
core processors. This enables a direct connection for a given dual-core processor to all other dual-core
processors but one in a 4-way configuration. The throughput of each bidirectional HyperTransport
link is 4 GB/s in each direction. Each node has its own on-chip memory controller and is connected to
its own memory.
HyperTransport™ links. Each processor has one bidirectional HyperTransport link that is dedicated
to I/O and two bidirectional coherent HyperTransport links that are used to connect to two other dual-
core processors. This enables a direct connection for a given dual-core processor to all other dual-core
processors but one in a 4-way configuration. The throughput of each bidirectional HyperTransport
link is 4 GB/s in each direction. Each node has its own on-chip memory controller and is connected to
its own memory.
As shown in Figure 1 on page 14, the processors (also called nodes) are numbered N0, N1, N3 and
N2 clockwise from the top left. Each Node has two cores—labeled C0 and C1 respectively [
N2 clockwise from the top left. Each Node has two cores—labeled C0 and C1 respectively [
1
].