AMD amd64 architecture User Manual
86
General-Purpose Programming
AMD64 Technology
24592—Rev. 3.15—November 2009
Branches to 64-Bit Offsets.
Because immediates are generally limited to 32 bits, the only way a full
64-bit absolute RIP can be specified in 64-bit mode is with an indirect branch. For this reason, direct
forms of far branches are invalid in 64-bit mode.
forms of far branches are invalid in 64-bit mode.
3.7.10 Interrupts and Exceptions
Interrupts and exceptions are a form of control transfer operation. They are used to call special system-
service routines, called interrupt handlers, which are designed to respond to the interrupt or exception
condition. Pointers to the interrupt handlers are stored by the operating system in an interrupt-
descriptor table, or IDT. In legacy real mode, the IDT contains an array of 4-byte far pointers to
interrupt handlers. In legacy protected mode, the IDT contains an array of 8-byte gate descriptors. In
long mode, the gate descriptors are 16 bytes. Interrupt gates, task gates, and trap gates can be stored in
the IDT, but not call gates.
service routines, called interrupt handlers, which are designed to respond to the interrupt or exception
condition. Pointers to the interrupt handlers are stored by the operating system in an interrupt-
descriptor table, or IDT. In legacy real mode, the IDT contains an array of 4-byte far pointers to
interrupt handlers. In legacy protected mode, the IDT contains an array of 8-byte gate descriptors. In
long mode, the gate descriptors are 16 bytes. Interrupt gates, task gates, and trap gates can be stored in
the IDT, but not call gates.
Interrupt handlers are usually privileged software because they typically require access to restricted
system resources. System software is responsible for creating the interrupt gates and storing them in
the IDT. “Exceptions and Interrupts” in Volume 2 contains detailed information on the interrupt
mechanism and the requirements on system software for managing the mechanism.
system resources. System software is responsible for creating the interrupt gates and storing them in
the IDT. “Exceptions and Interrupts” in Volume 2 contains detailed information on the interrupt
mechanism and the requirements on system software for managing the mechanism.
The IDT is indexed using the interrupt number, or vector. How the vector is specified depends on the
source, as described below. The first 32 of the available 256 interrupt vectors are reserved for internal
use by the processor—for exceptions (as described below) and other purposes.
source, as described below. The first 32 of the available 256 interrupt vectors are reserved for internal
use by the processor—for exceptions (as described below) and other purposes.
Interrupts are caused either by software or hardware. The INT, INT3, and INTO instructions
implement a software interrupt by calling an interrupt handler directly. These are general-purpose
(privilege-level-3) instructions. The operand of the INT instruction is an immediate byte value
specifying the interrupt vector used to index the IDT. INT3 and INTO are specific forms of software
interrupts used to call interrupt 3 and interrupt 4, respectively. External interrupts are produced by
system logic which passes the IDT index to the processor via input signals. External interrupts can be
either maskable or non-maskable.
implement a software interrupt by calling an interrupt handler directly. These are general-purpose
(privilege-level-3) instructions. The operand of the INT instruction is an immediate byte value
specifying the interrupt vector used to index the IDT. INT3 and INTO are specific forms of software
interrupts used to call interrupt 3 and interrupt 4, respectively. External interrupts are produced by
system logic which passes the IDT index to the processor via input signals. External interrupts can be
either maskable or non-maskable.
Exceptions usually occur as a result of software execution errors or other internal-processor errors.
Exceptions can also occur in non-error situations, such as debug-program single-stepping or address-
breakpoint detection. In the case of exceptions, the processor produces the IDT index based on the
detected condition. The handlers for interrupts and exceptions are identical for a given vector.
Exceptions can also occur in non-error situations, such as debug-program single-stepping or address-
breakpoint detection. In the case of exceptions, the processor produces the IDT index based on the
detected condition. The handlers for interrupts and exceptions are identical for a given vector.
The processor’s response to an exception depends on the type of the exception. For all exceptions
except 128-bit-media and x87 floating-point exceptions, control automatically transfers to the handler
(or service routine) for that exception, as defined by the exceptions vector. For 128-bit-media and x87
floating-point exceptions, there is both a masked and unmasked response. When unmasked, these
exceptions invoke their exception handler. When masked, a default masked response is provided
instead of invoking the exception handler.
except 128-bit-media and x87 floating-point exceptions, control automatically transfers to the handler
(or service routine) for that exception, as defined by the exceptions vector. For 128-bit-media and x87
floating-point exceptions, there is both a masked and unmasked response. When unmasked, these
exceptions invoke their exception handler. When masked, a default masked response is provided
instead of invoking the exception handler.
Exceptions and software-initiated interrupts occur synchronously with respect to the processor clock.
There are three types of exceptions:
There are three types of exceptions: