AMD amd64 architecture User Manual
Memory Model
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24592—Rev. 3.15—November 2009
AMD64 Technology
truncated to the effective-address size of the current mode (64-bit mode or compatibility mode), as
overridden by any address-size prefix. The result is then zero-extended to the full 64-bit address width.
overridden by any address-size prefix. The result is then zero-extended to the full 64-bit address width.
Because of this, 16-bit and 32-bit applications running in compatibility mode can access only the low
4GB of the long-mode virtual-address space. Likewise, a 32-bit address generated in 64-bit mode can
access only the low 4GB of the long-mode virtual-address space.
4GB of the long-mode virtual-address space. Likewise, a 32-bit address generated in 64-bit mode can
access only the low 4GB of the long-mode virtual-address space.
Displacements and Immediates.
In general, the maximum size of address displacements and
immediate operands is 32 bits. They can be 8, 16, or 32 bits in size, depending on the instruction or, for
displacements, the effective address size. In 64-bit mode, displacements are sign-extended to 64 bits
during use, but their actual size (for value representation) remains a maximum of 32 bits. The same is
true for immediates in 64-bit mode, when the operand size is 64 bits. However, support is provided in
64-bit mode for some 64-bit displacement and immediate forms of the MOV instruction.
displacements, the effective address size. In 64-bit mode, displacements are sign-extended to 64 bits
during use, but their actual size (for value representation) remains a maximum of 32 bits. The same is
true for immediates in 64-bit mode, when the operand size is 64 bits. However, support is provided in
64-bit mode for some 64-bit displacement and immediate forms of the MOV instruction.
FS and GS as Base of Address Calculation.
In 64-bit mode, the FS and GS segment-base registers
(unlike the DS, ES, and SS segment-base registers) can be used as non-zero data-segment base
registers for address calculations, as described in “Segmented Virtual Memory” in Volume 2. 64-bit
mode assumes all other data-segment registers (DS, ES, and SS) have a base address of 0.
registers for address calculations, as described in “Segmented Virtual Memory” in Volume 2. 64-bit
mode assumes all other data-segment registers (DS, ES, and SS) have a base address of 0.
2.2.4 Address-Size Prefix
The default address size of an instruction is determined by the default-size (D) bit and long-mode (L)
bit in the current code-segment descriptor (for details, see “Segmented Virtual Memory” in Volume 2).Application software can override the default address size in any operating mode by using the 67h
address-size instruction prefix byte. The address-size prefix allows mixing 32-bit and 64-bit addresses
on an instruction-by-instruction basis.
bit in the current code-segment descriptor (for details, see “Segmented Virtual Memory” in Volume 2).Application software can override the default address size in any operating mode by using the 67h
address-size instruction prefix byte. The address-size prefix allows mixing 32-bit and 64-bit addresses
on an instruction-by-instruction basis.
Table 2-1 on page 18 shows the effects of using the address-size prefix in all operating modes. In 64-
bit mode, the default address size is 64 bits. The address size can be overridden to 32 bits. 16-bit
addresses are not supported in 64-bit mode. In compatibility and legacy modes, the address-size prefix
works the same as in the legacy x86 architecture.
bit mode, the default address size is 64 bits. The address size can be overridden to 32 bits. 16-bit
addresses are not supported in 64-bit mode. In compatibility and legacy modes, the address-size prefix
works the same as in the legacy x86 architecture.