AMD amd64 architecture User Manual
20
Memory Model
AMD64 Technology
24592—Rev. 3.15—November 2009
Figure 2-9.
Stack Pointer Mechanism
In typical APIs, the stack-frame base pointer and the stack pointer point to the same location before a
procedure call (the top-of-stack of the prior stack frame). After data is pushed onto the stack, the stack-
frame base pointer remains where it was and the stack pointer advances downward to the address
below the pushed data, where it becomes the new top-of-stack.
procedure call (the top-of-stack of the prior stack frame). After data is pushed onto the stack, the stack-
frame base pointer remains where it was and the stack pointer advances downward to the address
below the pushed data, where it becomes the new top-of-stack.
In legacy and compatibility modes, the default stack pointer size is 16 bits (SP) or 32 bits (ESP),
depending on the default-size (B) bit in the stack-segment descriptor, and multiple stacks can be
maintained in separate stack segments. In 64-bit mode, stack pointers are always 64 bits wide (RSP).
depending on the default-size (B) bit in the stack-segment descriptor, and multiple stacks can be
maintained in separate stack segments. In 64-bit mode, stack pointers are always 64 bits wide (RSP).
Further application-programming details on the stack mechanism are described in “Control Transfers”
on page 76. System-programming details on the stack segments are described in “Segmented VirtualMemory” in Volume 2.
on page 76. System-programming details on the stack segments are described in “Segmented VirtualMemory” in Volume 2.
2.5
Instruction Pointer
The instruction pointer is used in conjunction with the code-segment (CS) register to locate the next
instruction in memory. The instruction-pointer register contains the displacement (offset)—from the
base address of the current CS segment, or from address 0 in 64-bit mode—to the next instruction to be
executed. The pointer is incremented sequentially, except for branch instructions, as described in
“Control Transfers” on page 76.
instruction in memory. The instruction-pointer register contains the displacement (offset)—from the
base address of the current CS segment, or from address 0 in 64-bit mode—to the next instruction to be
executed. The pointer is incremented sequentially, except for branch instructions, as described in
“Control Transfers” on page 76.
In legacy and compatibility modes, the instruction pointer is a 16-bit (IP) or 32-bit (EIP) register. In
64-bit mode, the instruction pointer is extended to a 64-bit (RIP) register to support 64-bit offsets. The
case-sensitive acronym, rIP, is used to refer to any of these three instruction-pointer sizes, depending
on the software context.
64-bit mode, the instruction pointer is extended to a 64-bit (RIP) register to support 64-bit offsets. The
case-sensitive acronym, rIP, is used to refer to any of these three instruction-pointer sizes, depending
on the software context.
Figure 2-10 on page 21 shows the relationship between RIP, EIP, and IP. The 64-bit RIP can be used
for RIP-relative addressing, as described in “RIP-Relative Addressing” on page 18.
for RIP-relative addressing, as described in “RIP-Relative Addressing” on page 18.
513-110.eps
Stack-Segment (SS) Base Address
Stack-Frame Base Pointer (rBP)
and Stack Pointer (rSP)
Stack-Segment (SS) Base Address
Stack-Frame Base Pointer (rBP)
Stack Pointer (rSP)
passed data
Stack Frame Before Procedure Call
Stack Frame After Procedure Call