AMD amd64 architecture User Manual
66
General-Purpose Programming
AMD64 Technology
24592—Rev. 3.15—November 2009
See “Feature Detection” on page 74 for details about using the CPUID instruction. For a full
description of the CPUID instruction and its function codes, see “CPUID” in Volume 3 and the
CPUID Specification, order# 25481.
description of the CPUID instruction and its function codes, see “CPUID” in Volume 3 and the
CPUID Specification, order# 25481.
3.3.16 Cache and Memory Management
Applications can use the cache and memory-management instructions to control memory reads and
writes to influence the caching of read/write data. “Memory Optimization” on page 92 describes how
these instructions interact with the memory subsystem.
writes to influence the caching of read/write data. “Memory Optimization” on page 92 describes how
these instructions interact with the memory subsystem.
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LFENCE—Load Fence
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SFENCE—Store Fence
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MFENCE—Memory Fence
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PREFETCHlevel—Prefetch Data to Cache Level level
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PREFETCH—Prefetch L1 Data-Cache Line
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PREFETCHW—Prefetch L1 Data-Cache Line for Write
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CLFLUSH—Cache Line Invalidate
The LFENCE, SFENCE, and MFENCE instructions can be used to force ordering on memory
accesses. The order of memory accesses can be important when the reads and writes are to a memory-
mapped I/O device, and in multiprocessor environments where memory synchronization is required.
LFENCE affects ordering on memory reads, but not writes. SFENCE affects ordering on memory
writes, but not reads. MFENCE orders both memory reads and writes. These instructions do not take
operands. They are simply inserted between the memory references that are to be ordered. For details
about the fence instructions, see “Forcing Memory Order” on page 94.
accesses. The order of memory accesses can be important when the reads and writes are to a memory-
mapped I/O device, and in multiprocessor environments where memory synchronization is required.
LFENCE affects ordering on memory reads, but not writes. SFENCE affects ordering on memory
writes, but not reads. MFENCE orders both memory reads and writes. These instructions do not take
operands. They are simply inserted between the memory references that are to be ordered. For details
about the fence instructions, see “Forcing Memory Order” on page 94.
The PREFETCHlevel, PREFETCH, and PREFETCHW instructions load data from memory into one
or more cache levels. PREFETCHlevel loads a memory block into a specified level in the data-cache
hierarchy (including a non-temporal caching level). The size of the memory block is implementation
dependent. PREFETCH loads a cache line into the L1 data cache. PREFETCHW loads a cache line
into the L1 data cache and sets the cache line’s memory-coherency state to modified, in anticipation of
subsequent data writes to that line. (Both PREFETCH and PREFETCHW are 3DNow!™
instructions.) For details about the prefetch instructions, see “Cache-Control Instructions” on page 99.
For a description of MOESI memory-coherency states, see “Memory System” in Volume 2.
or more cache levels. PREFETCHlevel loads a memory block into a specified level in the data-cache
hierarchy (including a non-temporal caching level). The size of the memory block is implementation
dependent. PREFETCH loads a cache line into the L1 data cache. PREFETCHW loads a cache line
into the L1 data cache and sets the cache line’s memory-coherency state to modified, in anticipation of
subsequent data writes to that line. (Both PREFETCH and PREFETCHW are 3DNow!™
instructions.) For details about the prefetch instructions, see “Cache-Control Instructions” on page 99.
For a description of MOESI memory-coherency states, see “Memory System” in Volume 2.
The CLFLUSH instruction writes unsaved data back to memory for the specified cache line from all
processor caches, invalidates the specified cache, and causes the processor to send a bus cycle which
signals external caching devices to write back and invalidate their copies of the cache line. CLFLUSH
provides a finer-grained mechanism than the WBINVD instruction, which writes back and invalidates
all cache lines. Moreover, CLFLUSH can be used at all privilege levels, unlike WBINVD which can be
used only by system software running at privilege level 0.
processor caches, invalidates the specified cache, and causes the processor to send a bus cycle which
signals external caching devices to write back and invalidate their copies of the cache line. CLFLUSH
provides a finer-grained mechanism than the WBINVD instruction, which writes back and invalidates
all cache lines. Moreover, CLFLUSH can be used at all privilege levels, unlike WBINVD which can be
used only by system software running at privilege level 0.
3.3.17 No Operation
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NOP—No Operation