Nokia 6090 Service Manual

PAMS

Technical Documentation

NME–3

Technical  Information

Page 45

Issue 1  10/99

 The phase detector compares this signal with the reference signal divided
by the reference divider from the VCTCXO. The error signal generated by
the phase detector drives the charge pumps. The current pulses
generated by the charge pumps are integrated by the loop filter to
produce a control voltage for the UHF VCO. The settling time of the
synthesizer is defined by the loop filter component values. The channel
spacing is equal to the comparison frequency which is 200 KHz.

Figure 18.

 Phase locked loop , PLL

VCO

CHARGE

PUMP

PHASE

DET.

: R

f_out

LP

Kvco

Kd

M = A(P+1) + (N–A)P=

f ref

f_out /M

freq.

reference

    = NP+A

AFC–controlled VCTCXO

: M

The VHF PLL is also located in PLUSSA. There is a 16/17 ( P/P+1 ) dual
modulus prescaler, N and A dividers, reference divider, phase detector
and charge pumps. The VHF signal is generated by a discrete VCO
circuit. The VHF PLL works in the same way as the UHF PLL. The VHF
PLL operates at a fixed frequency (232 MHz) regardless of the traffic
channel frequencies. A frequency divider is used after the VHF VCO in
order to reduce phase noise.

Type

Linear, FDMA/TDMA

IF frequencies

1st 71 MHz, 2nd 13 MHz

LO frequencies

1st LO 1006 ... 1031 MHz, 2nd LO 58 MHz

Typical 3 dB bandwidth (reference noise band-

width)

+/– 90kHz

Sensitivity

min. – 104 dBm , S/N >8 dB

Total typical receiver voltage gain ( from antenna

to RX ADC )

88 dB

Receiver output level ( RF level –104 dBm )

50 mVpp ( typical balanced signal level of 13

MHz 

   IF in RF BB interface = input level to RX

ADCs )

Typical AGC dynamic range

50 dB

Accurate AGC control range

57 dB